synthesis report doubt1

Hi my doubt is now in synthesis report i got the report statiing

area is 100(+5) but actual area is 41 etc ...
what does thsi 41,5,100 indicates .

bye

In which synthesis tool did you get this report...

This is a FPGA tool. xilinx gives such informations in the synthesis report.
The tool estimates that of the total area(100) ur design requires 41%.
it shouldn't be of any problem to u.

Hi
yeah iam using Xilinx tools,i understand the same but i didn't get about (+5) in the statement,actually that made me to put in the forum,so plz answer for tht tooo.

hi vinod

its simple ... its an upper margin over the area constraint u specified....
as u said in the synth report u found

area is 100(+5) but actual area is 41

tht means u have allowed tool to place ur design over entire "100%" of the FPGA (this 100 is by default)... and tht the tool found out tht ur design can be fit into 41% area of the FPGA...

now had u had specified say 80% area (instead of 100)...and the tool finds out tht ur design is taking say 85% area ...then since margin is +5...so it'll consider tht the area constraint is met...otherwise if its more than 85% then it'll go for further optimization (frm area viewpoint) and will then tell u if the area constraint can be met or not....

i suppose this info will help u to some extent

for detailed study plz visit
h**p://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/xst/xst0039_6.html
and other related links....

cheers[/quote]