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Delay configuration completion by DLL

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Tetra

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I read in xilinx data sheets that I can delay the configuration of the FPGA until an internal DLL reach lock state how can I do that.
 

DLL macros have an external pin labeled "LOCKED". This pin shall remain in a low state until the dll generated clocks are stable (frequency and duty cycle).
 

I know that, so should I tie this pin to external output pin and control the ~INT pin to delay the DONE signal ?, or there is an internal methode ?
 

Sorry, I believe I didn´t understand you. If you want DONE pin to be high after DLL locks, you have a checkbox for that in the options for the program file generation (I belive it is in the Startup section).
 

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