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I used both extensively. The VHDL mode has a beautify buffer that fixes up all the indentations. It also has a create testbench.omara007 said:Yet, comparing some some modes to others, VHDL-mode is very poor compared to Verilog-Mode .. I'm not sure if there is something better for VHDL editing or not .. given being free
hdlcohen said:I used both extensively. The VHDL mode has a beautify buffer that fixes up all the indentations. It also has a create testbench.omara007 said:Yet, comparing some some modes to others, VHDL-mode is very poor compared to Verilog-Mode .. I'm not sure if there is something better for VHDL editing or not .. given being free
My copy of that is at
https://SystemVerilog.us/vhdl-mode.el
https://SystemVerilog.us/vhdl-mode.elc
Ben
I haven't used the AUTO feature of verilog. However, SystemVerilogmade life a lot easier on things like the port declaration, and sensitivity list (like the always_comb).omara007 said:Using VHDL-Mode, how do you handle things like changing IO for one block in the hierarchy, automatic declaration of signals, updating the sensitivity list of a process, etc ?
In Verilog-Mode, all these things can easily be done using AUTOs.