fundamental question about reset.

xilinx asynchronous reset

Generally, we can use two types of 'reset'.
The one is syncronous reset.
Another is asyncronous reset.
I have a fundamental question about this reset.

What is the purpose of two types' reset?
When do we have to adopt sync reset to the HDL?
When do we have to use async reset to the HDL?
Why do the two type of resets exist?

I do not expect an answer, whether 'clock' affects those two resets or not.

I appreciate it if u answer reasonably.

xilinx fpga + without use asynchronous reset

it's like you ask why is black different from white and say "no speak of colors plz!" IT is not reasonable!
......
for example, you dont want to let current execution be unfinished for reset condition. you want the periodic counter to enable some "overflow" pin after it reaches it overflowing condition and then RESET's itself synchronously. if the reset was Asynchronous you could not be sure of "overflow" release for use of other parts of circuit....
or you have some important interrupt(some master RESET of the whole system) that must override everythimg and reset at once....when it goes to application the clock will find it's REASONABLE meaning.

asynchronous rest vs asynchronous reset

assuming situation: I have 10000 bits counter 1HZ input clock and no async reset. How long should I wait, before counter rolls over.... Or I have few VHDL processes how I can syncronoze them withou async reset on power up??

fpga synchronous asynchronous reset false path

(Copied)

Resets and fail safe behavior:
Depending on the application, different types of resets may or may not be available. There may
be a synchronous and an asynchronous reset, there may only be one, or there may be none.
In any case, to ensure fail safe behavior, one of two things must be done, depending on the
type of reset:
Use an asynchronous reset. This ensures the FSM is always initialized to a known state
before the first clock transition and before normal operation commences. This has the
advantage of minimizing the next state logic by not having to decode any unused current state
values.
With no reset or a synchronous reset. When an asynchronous reset is unavailable, there is
no way of predicting the initial value of the state register flip-flops when the IC is powered up.
In the worst case scenario, it could power up and become stuck in an uncoded state. Therefore,
all 2n binary values must be decoded in the next state logic, whether they form part of the state
machine or not.

Hope this helps,

Pld4me

what is sync or async reset

Well

with an FPGA design insight,

First of all, You do not need the reset signal at all
( was that funny? )

Well , yes, all of the flip flops inside your fpga, have an initial state, this initial state can be indicated in the configuration bit file, for xilinx dev tools, you can simply use constraints editor to indicate the initial state of each of the important registers explicitly. So, although you put a reset input port in your design, you will not use it at all,

any how, as you say they are two options available for reset, for your fpga designs, reset path is usually set to false path, meaning that the timing for this path is not important at all. reset duration is always long, some near a second, and so during this period, all of the flip flops will go to their initial state, despite of the kind of reset you are using (sync or async )

generally, In my idea, there is no difference between these two kind of resets. However, I should note that the behaviour of Synthesis tool is too important in this case.

I remember long time ago, we had to use asynchronous reset , so that the synplify sythesis tool understand that it should use the reset input of the flip flops, otherwise synplify would implement reset at normal logic using look up tables. so you see here , the coding style ( sync ro async reset ) affect the amount of logic resource usage and the performance of the circuit

As you know, flip flops have hold time and setup time specs. The signal which enters a flip flop should obey these specs, Otherwise the flip flop can go unstable. So generally it seems that it is better for us to use a synchronous reset , But, originally the nature of reset signal is asynchronous, the user pushes a button and the reset is generated , the user does not know anything from the clock pulse inside our circuit, so , you should synchronize the incomming reset signal to your clock domain at the entrance to your circuit. Then you will use this synchronized reset signal in the rest of your circuits. ( personally I have never done this, but seems to be the safest way )

xilinx asynchronous reset signal constraint

The sequential circuits need a signal to enter an initial state that is reset.
Syn-reset signal is always sampled at the edge of clock while asyn-reset not.
I think the Synopsys on line document discussed such problem, you may refer to it.

reset state machine

if reset signal is noisy, to use syn-reset is a good anti-noise idea.

state machines synchronous reset xilinx

We should always use synchronous reset if you are using Xilinx Device. This is important to make sure design achieve highest performance. If using asynchronous reset, it may cause P&R hard to make routing. This is bad for high speed design. Asynchronous reset should use in low-speed design only if you wish to use aysnchronous reset. Bear in mind, you may have some trouble when asynchronous reset goes transition from high to low on positive edge of clock.

My advice is synchronous reset is the best for high speed performance design.
Please refer to Xilinx's white paper on high-speed design.


Thanks.

asynchronous reset constraint xilinx

Hi ..,

The syncronous reset is syncronized with the Clock, but there is a need for asyncroous reset for example when an external reset to the whole system is required :
One practical example is the machines like photocopier needs to be reseted either by te reset button or by the main power off. Also your computer when hangs up , there is a need to this asyncronous reset.

Generally in digital design you are dealing with the two types of inputs syncronous and Asyncronous ( mechanical devices generate this type of inputs)

I hope that i answered your Question, I will be happy to have comments about that and let me know if you have a different opinion.

Rashad

asynchronous nature of reset

Ok, so is it still true?

If I don't need fast-performance, will using asynchronous reset reduce hardware-resources (due to special async-reset path) ?

Do all FPGAs have the special asynchronous-reset hardware? Or just Altera/Xilinx?