Questions about how to use casex in Verilog

verilog casex

I read the IEEEstandard1364-2005 for Verilog HDL and came across these code:

The following is an example of the casex statement. It demonstrates an extreme case of how donot-
care conditions can be dynamically controlled during simulation. In this case, if r = 8'b01100110,
then the task stat2 is called.

reg [7:0] r, mask;
mask = 8'bx0x0x0x0;
casex (r ^ mask)
8'b001100xx: stat1;
8'b1100xx00: stat2;
8'b00xx0011: stat3;
8'bxx010100: stat4;
endcase

I just wonder if r^mask=00110011, then I think it satisfied the condition of stat1 and stat3, but I guess there should be just one statement being excuted,which statement will be excuted? stat1 or state3? Why? Thank you.

casex verilog

hi,

r^mask =x1x0x1x0 this would be the result for r=01100110 and mask=x0x0x0x0


so when it compare in the cases

the 1st choice is not satisfied becauseit would be like this
x1x0x1x0
001100xx

so they are not equal from left to right the 2,4,6th bits are not equal

in the 2nd choice
x1x0x1x0
1100xx00

see here every bit matches with the other bit so tghis choice is been selected

now lets see the third choce
x1x0x1xo
00xx0011

here in this case 2,6,8th bits are not matching so it cannot be selected
so this choice is not selected

now lets see the fourth choice
x1x0x1x0
xx010100

in this case the 4th bit is not matching so this choice is also not selected



so at last the choice is stat2 task being selected

i hope u got it if not post a reply so that i can help u

jamesqjf said:

I read the IEEEstandard1364-2005 for Verilog HDL and came across these code:

The following is an example of the casex statement. It demonstrates an extreme case of how donot-
care conditions can be dynamically controlled during simulation. In this case, if r = 8'b01100110,
then the task stat2 is called.

reg [7:0] r, mask;
mask = 8'bx0x0x0x0;
casex (r ^ mask)
8'b001100xx: stat1;
8'b1100xx00: stat2;
8'b00xx0011: stat3;
8'bxx010100: stat4;
endcase

I just wonder if r^mask=00110011, then I think it satisfied the condition of stat1 and stat3, but I guess there should be just one statement being excuted,which statement will be excuted? stat1 or state3? Why? Thank you.

Click to expand...

I think stat1 will be selected. Because there is priority in casex statement.