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Synthesis constraints

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Dr_MS

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set_max_transition

Hi,

Can anyone tell me more about the synthesis commands set_max_transition, set_clock_uncertainty and set_load. Specially how to estimate them for submicron technologies. Thanks in advance.
 

synthesis constraints

check snug doc or synopsys user manual for detail
 

synopsys set_max_transition

set_max_transition: it is one of design rule, it constrains the max transition time on clock;
set_clock_uncertainty: it accounts for clock skew;
set_load: Sets load attribute value on specified ports and nets.
 

synthesis setting constraints

Dr_MS said:
Hi,

Can anyone tell me more about the synthesis commands set_max_transition, set_clock_uncertainty and set_load. Specially how to estimate them for submicron technologies. Thanks in advance.
Click to expand...

this commands are used in pre-layout synthesis
set_max_transition is to set the max time period which is the clk turning time from high o to low or low to high. After layout, this command can be elided, because DC caculate the actual transition time based on routing and clock tree information.

set_clock_uncertainty is to leave a margin for both setup and hold time, it ensure a robust design

set_load sets a capacitive load to the design

I am also wandering how to estimate them , maybe it comes from some experience or some fixed specification which is summed up by others.
 

set_clock_uncertainty synopsys

set_max_transition: it is one of design rule, it constrains the max transition on input of the design (ideally it should be small);
set_clock_uncertainty: it s for uncertainity like Jitter, clock skew;
set_load: Sets load attribute value on outputs becoz for output its a load capacitance.
 

dc set_max_transition

The current synthesis tool can not estimate post-layout long wire delay very well for submicron technologies.

set_max_transition: smaller number can force synthesis tool to add more buffers to minimized the RC delay for the heavy loaded singal.
set_clock_uncertainty: bigger number can increase the setup time margin to help to overcome the difficulty of wilre delay estimation;
set_load: bigger number can force synthesis tool to take care output buffering and local buffering separately for a output signals.

Sometimes RTL coding change is required to help to address post-layout long wire delay issue.
 

synthesis set_load

all these constraints have close relation with your design,so when you set them you should firstly know your design spec
 

synthesis commands

This may help you a little......

all the best......
 

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