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In an clocked process, you don't put all other signals in sensitivity list. If suppose your flip-flop uses asynchronous reset, then you can add reset in the sensitivity list, nothing more.
hi,
If you are building a synchronize circuit the sensitivity list would consist only of clk. nothing else.
If you are building an Asynchronous circuit, i think you dont need to worry about the question you have asked since you can use multiple clk or multiphase clk(refering verilog).
I hope the above described would give a solution.
But as of you ask on having more than one edge triggered inputs in a sensitivity list.. and how the clk is identified...
my comment would be to check the condition of all the edge triggered inputs given in the sensitivity list inside the always block exept the clock input.
But i am not sure whether it would be synthesisable or not.
i think that the synthesis tool can take the signal with the largest fanout as the clock in case of multiple edge triggered inputs in large designs...please correct me if i am wrong..
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