Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Ask for help about multi-phase clock generation?

Status
Not open for further replies.
D

Davidy

Junior Member level 2
Joined
Sep 14, 2005
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,465
cmos digital multiphase clock -patent

I want to generate a multi-phase clock for swithed-capacitor circuit such as the figure below. The clock freq. is about 100kHz and the delay between phases is about several handred ns.

Can any one give me some advice?

88_1161177688.GIF
 

You can reference these papers, but limited information~

A Low Power 1.8V 4-Bit 400-MHz Flash ADC in0.18μ Digital CMOS

AN IMPROVED PHASE CLOCK GENERATOR FOR INTERLEAVED AND DOUBLE-SAMPLED SWITCHED-CAPACITOR CIRCUITS

A 14-b 20-MSamples/s CMOS Pipelined ADC


A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply

Also interested in the design technique of adc, mistdark@uestc.edu.cn.
 

    D

    Davidy

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top