steven852
Advanced Member level 4
I am having this timing problem and seek suggestions:
The pre-layout synthesis met all the timing. The layout tool (Encounter) had timing violations with wire model. The wire model used was not accurate enough so a post-layout timing analysis with PT (RC extraction with Star RC, SDC files, and routed netlist) was carried on. The post-layout timing analysis also not met. I don't know what step to work on to resolve this problem.
Anyone has suggestions?
Thanks.
The pre-layout synthesis met all the timing. The layout tool (Encounter) had timing violations with wire model. The wire model used was not accurate enough so a post-layout timing analysis with PT (RC extraction with Star RC, SDC files, and routed netlist) was carried on. The post-layout timing analysis also not met. I don't know what step to work on to resolve this problem.
Anyone has suggestions?
Thanks.
