Question:errors after lvs

The layout from SE, after I do lvs with Calibre, threr are over one hundred errors in lvs report, I don't know what's the problem? Can someone help me? Thanks!

here's some errors in lvs report:
CELL COMPARISON RESULTS
Error: Different numbers of ports (see below).
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.

LAYOUT CELL NAME: DFCLRBEHD
SOURCE CELL NAME: DFCLRBEHD
--------------------------------------------------------------------------------------------------------------

NUMBERS OF OBJECTS
------------------

Layout Source Component Type
------ ------ --------------
Ports: 15 8 *

Nets: 18 24 *

Instances: 10 18 * MN (4 pins)
4 18 * MP (4 pins)
------ ------
Total Inst: 14 36
INCORRECT NETS

DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************

1 Net 3 LD
-------------------------- --------------------------

** missing connection ** MMGI_141:g
** missing connection ** MMGI_220:g

M0(0.440,0.960):g ** unmatched connection **

** unmatched connection ** MMGI_221:g


--------------------------------------------------------------------------------------------------------------

2 Net 11 MPW
-------------------------- --------------------------

M13(11.040,1.840):g ** unmatched connection **
M10(5.820,2.240):s ** unmatched connection **
M9(11.040,0.360):g ** unmatched connection **
M6(6.150,0.400):s ** unmatched connection **

** unmatched connection ** MMGI_24:g
** unmatched connection ** MMGI_16:s
** unmatched connection ** MMGI6:s
** unmatched connection ** MMGI_142:g
** unmatched connection ** MMGI8:g
** unmatched connection ** MMGI_21:s
** unmatched connection ** MMGI3:s
5 Net 1 ** no similar net **

--------------------------------------------------------------------------------------------------------------

6 Net 2 ** no similar net **

--------------------------------------------------------------------------------------------------------------

7 Net 5 ** no similar net **

hello siboy

from the errors i can say that, the instances u have used are diff in source and layout, for example may be in schematic u used a low vt and in layout used a high vt .. and alos see if u have shorted the bulk of PMos to vdd and nmos to grd .. check that and tell if u still have errors

suresh

What liborary you used in you carlibre?

i am sorry... actually there are errors in instances also ..
please check the number of instances alos .. i guess u declared a dff no of instances. and alos it shows connectivity errroe .. let me know if u have DRC and did it had any errors ... .

I have done drc, it had only a few metal-to-metal widths errors, and I had corrected it. Can it be SE problem or I need do SE again?

Added after 5 minutes:

stormwolf said:

What liborary you used in you carlibre?

Click to expand...

I use the verilog file after SE, and do v2lvs in calibre .

i am sorry but ,, i am not aware of wat this SC is . can u please let me abt this .. i make layouts using cadence nad LVS using calibre .. so please let me knw abt this so that I can alos improve mu knowledge abt this

suresh

I don't have too much experience on Calibre LVS but see if this can help: run a separated LVS on the cells that have errors see what the errors are.

research235 said:

i am sorry but ,, i am not aware of wat this SC is . can u please let me abt this .. i make layouts using cadence nad LVS using calibre .. so please let me knw abt this so that I can alos improve mu knowledge abt this

suresh

Click to expand...

I also do layout with cadence:SE(Silicon Ensemble), and do LVS with calibre. I don't know which steps the errors are from: DC ,SE or LVS? My circuit is just some adders and some other gates.

Added after 1 minutes:

steven852 said:

I don't have too much experience on Calibre LVS but see if this can help: run a separated LVS on the cells that have errors see what the errors are.

Click to expand...

I had done this, and it has no errors.
Thanks all the same .

ok, if there is no error on the cells, then you can narrow down by doing this: add vdd! and gnd! on VerilogIn (I assume you have used it). Also, put vdd and gnd on your schematic view, ie., build a complete circuit. After this, is there any error?

since it shows instance mismatch.. you get know the instance it denotes and try to run separately.. that may clearly show u the problem.. one more thing is check whether you have mapped all instance.. because the tool thing as black box for child modules if they are mapped properly.. and it will show problem..

I used to get instance mismatch when i forget to add some module but they are portmapped.. mainly because of instance mismatch you get other errors like no of pins...


regards
Shankar

I found in my spice netlis from layout, some cells missed nmos transitors, and some cells missed pmos transistors. But in my layout, I can see all these transistors. For example, a NAND2 with 2 nmos and 2 pmos transistors, but in the spice from layout, there are only 2 pmos transistors. I don't know why. When I do lvs just for the NAND2 cell, it has no errors.