treehugger
Member level 2
adc placement setting
hi,
sorry guys, this is an ameturish (and a bit long) question. however i need help:
i have to design an array of DACs (operating around 50KHz) which will drive an array of large capacitors.
these DACs should be placed as close as possible to the capacitive array (i dont know exactly why? is it to prevent any degradation of the waveform due to coupling etc? please illuminate me about this). since design specs require that DACs to be placed as close as possible to the capacitive array, it turns out that these DACs should be of 10µ width. also these specs require that DACs should have low DNL (differential non-linearity) and INL (integral non-linearity). my initial investigation of the topic revealed that keeping DNL&INL requires a compromise involving chip area. that makes me uneasy and hopeless, since i believe that current mirrors, resistors, decoders and latches wont fit in 10µ width.
so.. instead of striving hard to ensure matching between transistors (or resistors) by employing techniques like current mirrors or layout structures like common-centroid, i have decided to have just one big transistor having a good (and wide) capability of sourcing current to the output op-amp. And the analog output of the op-amp will be feed back to the driving processor (that processor is also supplying digital data to the DAC array), so that when the desired voltage level reached sourcing transistor will stop increasing the supplied current. this design clearly involves an ADC in the feedback loop, and here comes the question:
do you think that this ADC in the feedback loop should be placed close to the driven capacitor array? and why?!
(i wonder if i made myself clear, sorry for bad handling of english)
thanks in advance.
hi,
sorry guys, this is an ameturish (and a bit long) question. however i need help:
i have to design an array of DACs (operating around 50KHz) which will drive an array of large capacitors.
these DACs should be placed as close as possible to the capacitive array (i dont know exactly why? is it to prevent any degradation of the waveform due to coupling etc? please illuminate me about this). since design specs require that DACs to be placed as close as possible to the capacitive array, it turns out that these DACs should be of 10µ width. also these specs require that DACs should have low DNL (differential non-linearity) and INL (integral non-linearity). my initial investigation of the topic revealed that keeping DNL&INL requires a compromise involving chip area. that makes me uneasy and hopeless, since i believe that current mirrors, resistors, decoders and latches wont fit in 10µ width.
so.. instead of striving hard to ensure matching between transistors (or resistors) by employing techniques like current mirrors or layout structures like common-centroid, i have decided to have just one big transistor having a good (and wide) capability of sourcing current to the output op-amp. And the analog output of the op-amp will be feed back to the driving processor (that processor is also supplying digital data to the DAC array), so that when the desired voltage level reached sourcing transistor will stop increasing the supplied current. this design clearly involves an ADC in the feedback loop, and here comes the question:
do you think that this ADC in the feedback loop should be placed close to the driven capacitor array? and why?!
(i wonder if i made myself clear, sorry for bad handling of english)
thanks in advance.