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Hi !
In my experience , The width of power ring ( core ring ) is as wide as possible but there must be have no wire-width violations !
All most my projects , I usually using maximum-wire-width rule in library for power coring !
i think we need to consider the total power for our design, we get this total power from synthesis part,with this value we calculate the current.. then we find out what is density for metal we use for power ring, from that we can calculate the width..
The width of the power ring depends upon the power consumption of the Block (or chip).
For Eg : If the power consumption of a block is say 300mw , then divide it into 4 parts. we get 75 mw on each side. based on this assumption we go ahead and calculate the width of the power lines.
Actually the width of the power lines are calculated using the EM Analysis.
I consider the description of "aifi" hears resonable. Certainly, the width is as wide as good, but excessive width will waste the area, so I feel we should work-out a appropriate value.
If you zoom full on the chip, you should be able to see the core power ring clearly, but not too thick. It is like looking at a door, you should see the door frame.
After saying that, if you are using 6 layers or more, consider overlapping two ring. If you use 0.25um or smaller technology, it is likely that you need more than one ring as the max metal wide is too little for the core ring.
For caliculating the power or ground width , I saw the following formulae in some PDF.
Power/Gnd width = Length of wire * Sum (all transistors
connected to wire) / 3*10 power6 lambda (very approximate)
But I too am not sure why 3*10 power6 lambda is used. It will be great if anyone can share some detailed data on how to decide the power width and factors affecting
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