Help on Verilog-HDL error: found pins functioning as undefined clocks/memory

Hi, folks.
I have encountered a problem which is plaguing my brain.
here is the information I got when I compiling the code:

Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "Clock" is an undefined clock

background: I am using Clock as a sequential clock signal in an always statement.
how can I get rid of this warning?

Thanks a lot!

Help on Verilog-HDL

u have to define any signal before you use it.
I guess you miss the statement: input Clock;

Help on Verilog-HDL

Show us a small code example, so maybe we can see what's going wrong.

Re: Help on Verilog-HDL

Thanks for your replies, here is an example.

module DataReader (DataStored,AddSel, DReaded, clk);

parameter ADD00=2'b00, ADD01=2'b01, ADD10=2'b10, ADD11=2'b11;

input [3:0] DataStored;
input [1:0] AddSel;
input clk;
output DReaded;

reg [1:0] Selsign;
reg SeleData;

always @ (AddSel)
Selsign=AddSel;

always @ (posedge clk)
case (Selsign)
ADD00:
SeleData<=DataStored[0];
ADD01:
SeleData<=DataStored[1];
ADD10:
SeleData<=DataStored[2];
ADD11:
SeleData<=DataStored[3];
default:
SeleData<=1'bx;
endcase
assign DReaded = SeleData;
endmodule
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Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock

Re: Help on Verilog-HDL

Checkout with this code!

Help on Verilog-HDL

I've never used Altera Quartus, but I see that exact warning message described in the "Quartus II Timing Analysis" manual. Maybe you are suppose to tell your tools that clk is a clock.

This looks suspicious. What are you trying to do?
input [1:0] AddSel;
reg [1:0] Selsign;
always @ (AddSel)
Selsign=AddSel;

Also, that case statement isn't really necessary.

Help on Verilog-HDL

when altera quartus write this messages
("Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "Clock" is an undefined clock")
in mean, that you need to use the quartus assignments (map the "Clock" port to the one of the clk pin of the fpga)

Re: Help on Verilog-HDL

hi, my friends
This code is used as an example of "how case statement conducts its mission?"
I guess that the case statement is for this purpose.Apparently, it is not the optimized one.
I just feel confused about the warning.

bpu, so you means it doesn't matter wheter the warning comes or not, if we only simulates our code, not download it into FPGAs.