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Need help for modeling a delay locked loop in simulink

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Alles Gute

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delay lock loop modeling

I have been trying to model a dll in simulink but to no results.
My problem is modeling the voltage controlled delay line. I tried to use variable transport delay. But it didn't work well.

Can anybody give me an example of modeling DLL or some materials related to that?

Regards,
Alles Gute
 

delay line simulink

i think systemview is better in simulation of PLL and DLLs
MATLAB has a DLL demo on communication blockset
 

delay locked loop matlab

Hi,mkhafaji:
What is the version of your Matlab? I use 7.0.1 and I can find only PLL model in communication blockset.

Alles Gute
 

circular buffer simulink

The Simulink block "Variable Transport Delay" is found in 6.5 and 7.0 at least and could model a DLL.

The problem could be that the "Variable Transport Delay" uses a discrete time circular buffer. That is to allow logic, real and complex values to path at the input at a higher rate than the delay time. That limit time resolution to discrete time steps and is overkill for the application.

You should use an integrator where the integration constant is multiplied with the input signal and the integrator integrate up to a threshold and then trigger a simple register and reset. The integration start with the incoming of a new edge. The register path this signal to output if the integrator reach the level.
 

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    Alles Gute

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transport delay simulink

Hi,

I too need the simulink modelling and simulation of digital delay locked loop (DLLs). Can anyone post or upload some design concepts and examples using simulink.
 

como funciona+transport delay+simulink

Hai,


Can anyone send me some good papers on digital delay locked loop ,which can be used for modelling and simulation using simulink or matlab or both.


Any help would be appreciated !
 

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