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what's the error in my vhdl code?why so much latch?

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lzh08

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warning: found combinational loop of 1 nodes

library ieee;
use ieee.std_logic_1164.all;

ENTITY MCU IS
PORT
(
nDataStrobe : IN Std_Logic;
nAddrStrobe : IN Std_Logic;
nWri : IN Std_Logic;
nReset : IN Std_Logic;
Data : INOUT Std_Logic_Vector(7 DOWNTO 0);
nWait : OUT Std_Logic;
nAck : OUT Std_Logic;

SysClk : in Std_Logic;
Reset : in Std_Logic
);
END MCU;

ARCHITECTURE Action OF MCU IS
TYPE State IS (Idle, DataRead, DataWrite, AddrRead, AddrWrite,
DataReadEnd, DataWriteEnd, AddrReadEnd, AddrWriteEnd);
SIGNAL Cur_State, Next_State:State := Idle;
SIGNAL RegDataTemp : std_logic_vector(7 downto 0);
SIGNAL RegAddrTemp : std_logic_vector(7 downto 0);

BEGIN
PROCESS(Cur_State, nDataStrobe, nWri, nAddrStrobe, RegDataTemp, RegAddrTemp,Data)
begin
nWait <= '0';
case Cur_State is
when Idle => nWait <= '0';
if ((nWri = '1') and (nDataStrobe = '0')) then
Next_State <= DataRead;
elsif ((nWri = '0') and (nDataStrobe = '0')) then
Next_State <= DataWrite;
elsif ((nWri = '1') and (nAddrStrobe = '0')) then
Next_State <= AddrRead;
elsif ((nWri = '0') and (nAddrStrobe = '0')) then
Next_State <= AddrWrite;
else
Next_State <= Idle;
end if;
when DataRead => Data <= RegDataTemp;
nWait <= '1';
Next_State <= DataReadEnd;
when DataWrite => RegDataTemp <= Data;
nWait <= '1';
Next_State <= DataWriteEnd;
when AddrRead => Data <= RegAddrTemp;
nWait <= '1';
Next_State <= AddrReadEnd;
when AddrWrite => RegAddrTemp <= Data;
nWait <= '1';
Next_State <= AddrWriteEnd;
when DataReadEnd => if (nDataStrobe = '1') then
nWait <= '0';
Next_State <= Idle;
else
Next_State <= DataReadEnd;
end if;
when AddrReadEnd => if (nAddrStrobe = '1') then
nWait <= '0';
Next_State <= Idle;
else
Next_State <= AddrReadEnd;
end if;
when DataWriteEnd => if ((nWri = '1') and (nDataStrobe = '1') ) then
nWait <= '0';
Next_State <= Idle;
else
Next_State <= DataWriteEnd;
end if;
when AddrWriteEnd => if ((nWri = '1') and (nAddrStrobe = '1') ) then
nWait <= '0';
Next_State <= Idle;
else
Next_State <= AddrWriteEnd;
end if;
when others => Next_State <= Idle;
end case;
end process;

process(Reset, SysClk)
begin
if Reset = '0' then
Cur_State <= Idle;
elsif Rising_Edge(SysClk) then
Cur_State <= Next_State;
end if;
end process;
end Action;
Warning: VHDL Process Statement warning at MCU.VHD(28): signal or variable "Data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "Data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at MCU.VHD(28): signal or variable "RegDataTemp" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "RegDataTemp" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at MCU.VHD(28): signal or variable "RegAddrTemp" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "RegAddrTemp" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Output port "nAck" at MCU.VHD(13) has no driver
Warning: Latch Data[0]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[1]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[2]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[3]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[4]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[5]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[6]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: Latch Data[7]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal Cur_State.addrread
Warning: TRI or OPNDRN buffers permanently enabled
Warning: Node "Data[0]~8"
Warning: Node "Data[1]~9"
Warning: Node "Data[2]~10"
Warning: Node "Data[3]~11"
Warning: Node "Data[4]~12"
Warning: Node "Data[5]~13"
Warning: Node "Data[6]~14"
Warning: Node "Data[7]~15"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "nAck" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "nReset"
Warning: The following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info: Pin Data[0] has a permanently enabled output enable
Info: Pin Data[1] has a permanently enabled output enable
Info: Pin Data[2] has a permanently enabled output enable
Info: Pin Data[3] has a permanently enabled output enable
Info: Pin Data[4] has a permanently enabled output enable
Info: Pin Data[5] has a permanently enabled output enable
Info: Pin Data[6] has a permanently enabled output enable
Info: Pin Data[7] has a permanently enabled output enable
Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin nAck has GND driving its datain port
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "RegDataTemp[0]" is a latch
Warning: Node "RegAddrTemp[0]" is a latch
Warning: Node "Data[0]$latch" is a latch
Warning: Node "RegDataTemp[1]" is a latch
Warning: Node "RegAddrTemp[1]" is a latch
Warning: Node "Data[1]$latch" is a latch
Warning: Node "RegDataTemp[2]" is a latch
Warning: Node "RegAddrTemp[2]" is a latch
Warning: Node "Data[2]$latch" is a latch
Warning: Node "RegDataTemp[3]" is a latch
Warning: Node "RegAddrTemp[3]" is a latch
Warning: Node "Data[3]$latch" is a latch
Warning: Node "RegAddrTemp[4]" is a latch
Warning: Node "RegDataTemp[4]" is a latch
Warning: Node "Data[4]$latch" is a latch
Warning: Node "RegAddrTemp[5]" is a latch
Warning: Node "RegDataTemp[5]" is a latch
Warning: Node "Data[5]$latch" is a latch
Warning: Node "RegDataTemp[6]" is a latch
Warning: Node "RegAddrTemp[6]" is a latch

Warning: Node "Data[6]$latch" is a latch
Warning: Node "RegAddrTemp[7]" is a latch
Warning: Node "RegDataTemp[7]" is a latch
Warning: Node "Data[7]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "SysClk" is an undefined clock
Code:
Code:
 

latch has unsafe behavior

Hi, you code is difficult to read. Please edit your message, highlight the code section, press the "Code" button, then the "Submit" button. That inserts tags that preserve your formatting.
 

warning: found combinational loop of 1 nodes

It looks like you're trying to update a register in an unclocked, asynchronous process. That leads to a latched design.
 

assuming node is an undefined clock

Just insert the three lines of code written at the beginning of your first process if u dont want to have latches in u r design :

RegDataTemp <= (OTHERS => '0');
RegAddrTemp <= (OTHERS => '0');
Data <= (OTHERS => '0');

Regards,
dcreddy1980
 

warning: node is a latch

dcreddy1980 said:
Just insert the three lines of code written at the beginning of your first process if u dont want to have latches in u r design :

RegDataTemp <= (OTHERS => '0');
RegAddrTemp <= (OTHERS => '0');
Data <= (OTHERS => '0');
Click to expand...
Although that removes the latches, it does not create the registers that are expected. The design, as it stands, is a latch-oriented design. The warnings about latches will need to be turned off (from some software option) or ignored.

One fault is that when data is input, the output data is not disconnected from the bidirectional bus by using the 'Z' state. The default for the data bus should be Data <= (others => 'Z'); Without the disconnect, Data used as input will be affected by latchings of or assignments to Data, and some of the messages are related to this. Setting the register defaults to 0 (or any other default value) means the registers will not retain data - I believe that isn't desired in this design.

lzh08 said:
Code: 
library ieee;
use ieee.std_logic_1164.all;

ENTITY MCU IS
PORT
(
    nDataStrobe : IN Std_Logic;                   
    nAddrStrobe : IN Std_Logic;                        
    nWri        : IN Std_Logic;                        
    nReset      : IN Std_Logic;                      
    Data        : INOUT Std_Logic_Vector(7 DOWNTO 0); 
    nWait       : OUT Std_Logic;                      
    nAck        : OUT Std_Logic;                     

    SysClk      : in Std_Logic;
    Reset       : in Std_Logic                   
);
END MCU;

ARCHITECTURE Action OF MCU IS
TYPE State IS (Idle, DataRead, DataWrite, AddrRead, AddrWrite,
               DataReadEnd, DataWriteEnd, AddrReadEnd, AddrWriteEnd);          
SIGNAL Cur_State, Next_State:State := Idle;
SIGNAL RegDataTemp : std_logic_vector(7 downto 0);
SIGNAL RegAddrTemp : std_logic_vector(7 downto 0);

BEGIN
PROCESS(Cur_State, nDataStrobe, nWri, nAddrStrobe, RegDataTemp, RegAddrTemp,Data)     
begin
    nWait <= '0';
    case Cur_State is   
    when Idle => nWait <= '0';
                 if ((nWri = '1') and (nDataStrobe = '0')) then
                     Next_State <= DataRead;
                 elsif ((nWri = '0') and (nDataStrobe = '0')) then
                     Next_State <= DataWrite;
                 elsif ((nWri = '1') and (nAddrStrobe = '0')) then
                     Next_State <= AddrRead;
                 elsif ((nWri = '0') and (nAddrStrobe = '0')) then
                     Next_State <= AddrWrite;
                 else
                     Next_State <= Idle;   
                 end if;
    when DataRead  => Data <= RegDataTemp;
                      nWait <= '1';
                      Next_State <= DataReadEnd;
    when DataWrite => RegDataTemp <= Data;
                      nWait <= '1';
                      Next_State <= DataWriteEnd;
    when AddrRead  => Data <= RegAddrTemp;
                      nWait <= '1';
                      Next_State <= AddrReadEnd;
    when AddrWrite => RegAddrTemp <= Data;
                      nWait <= '1';
                      Next_State <= AddrWriteEnd;
    when DataReadEnd => if (nDataStrobe = '1') then
                            nWait <= '0';
                            Next_State <= Idle;
                        else
                            Next_State <= DataReadEnd;
                        end if;   
    when AddrReadEnd => if (nAddrStrobe = '1') then
                            nWait <= '0';
                            Next_State <= Idle;
                        else
                            Next_State <= AddrReadEnd;
                        end if;   
    when DataWriteEnd => if ((nWri = '1') and (nDataStrobe = '1') ) then
                             nWait <= '0';
                             Next_State <= Idle;
                         else
                             Next_State <= DataWriteEnd;  
                         end if;                       
    when AddrWriteEnd => if ((nWri = '1') and (nAddrStrobe = '1') ) then
                             nWait <= '0';
                             Next_State <= Idle;
                         else
                             Next_State <= AddrWriteEnd;                        
                         end if;
    when others => Next_State <= Idle;
    end case;                    
end process;

process(Reset, SysClk)        
begin
    if Reset = '0' then
        Cur_State <= Idle;
    elsif Rising_Edge(SysClk) then
        Cur_State <= Next_State;
    end if;
end process;
end Action;
Click to expand...
 

vhdl latch

how to correct it?give a way,thx
 

pin has gnd driving its datain port

What do you want to correct?
Do you want to eliminate latches, as well as make the design work?
Or do you just want it to work?
 

register vhdl code latch

want to eliminate latches and make the design work
 

vhdl found combinational loop

I would suggest removing these register updates from the FSM and putting them in a different process.

RegDataTemp <= Data;
RegAddrTemp <= Data;

You can then condition them with a clock event, so that they are not latched but clocked. Create a clock enable signal for each of them, and control the enable signal from the FSM.

I normally put each register in a separate process, but they can be combined into one. The template I use for a clocked register with an enable signal is ...

Code: 
U_REGISTER_NAME: process (clock_name)
begin
    if rising_edge(clock_name) then
        if register_clock_enable_signal_name = '1' then
            register_output_signal_name <= signal_name_or_expression;
        end if;
    end if;
end process;
You also need to have

Data <= (others => 'Z');

as a default in the FSM.
 

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