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How to reduce the “response time High to Low”？

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holddreams

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For a NMOS open-drain comparator circuit,

how to reduce the “Response time High to Low”？

Thanks.
 

enlarge the w/l of nmos
 

Re: How to reduce the “response time High to Low”&#65311

the more u increase w/l will make your layout area large.so think before u design, have a nice day
 

If the issue is fall-time, then you may consider using a number of well dimention inverters before the last MOS
 

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