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verilog code for control signal(urgent)

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ravindra kalla

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hi,

i want to generet a contro signal.which should be high after 256 clock cycle(one time) after that it should high after 128 cycle(two times).

please suggest for this
 

I normally use a counter for that sort of thing.

You didn't say what starts the sequence, or what happens after the sequence ends. I'm also unsure what you mean by "one time" and "two times". I'm guessing you want pulses at t=256, t=384, and t=512.

How about this? You may want to add a reset input.
Code: 
module top (clk, start, control);
  input         clk, start;
  reg     [8:0] count = 0;
  output reg    control = 0;

  always @(posedge clk) begin
    count <= count + (start | (count != 0));
    control <= (count == 256-1) | (count == 384-1) | (count == 512-1);
  end
endmodule
Brief explanation:

"count" is a 9-bit up counter. It is initialized to zero. The counter increments only when "start" is true, or "count" is non-zero. That means a "start" pulse will initiate counting, and it will continue counting until it wraps around to zero, which occurs after 512 clocks. Then "count" will wait at zero for the next "start" pulse.

"control" is true only when count equals 256 or 384 or 512.


A "reset" input may not be necessary for your application, because this counter will reset itself within 512 clocks no matter what its initial state. However if you need a reset input, here is a synchronous reset. (I'm an FPGA guy who doesn't like asynchronous resets.):

Code: 
module top (clk, reset, start, control);
  input         clk, reset, start;
  reg     [8:0] count = 0;
  output reg    control = 0;

  always @(posedge clk) begin
    count <= reset ? 0 : count + (start | (count != 0));
    control <= reset ? 0 : (count == 256-1) | (count == 384-1) | (count == 512-1);
  end
endmodule
 

This mainly relates to one FSM implementation, provided you correctly specify the design behaviro, and the correct RTL description can be achieved!
 

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