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Need Verilog code for 1 signal for 1 period after 16 clock cycle

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ravindra kalla

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hi
i m writing a verilog code on that 1 controle signal should be there which will active after 16 clock cycle and only for one clock period.This control signal is used for select line of MUX.So that MUX
will select value from x(suppose) up to 16 clock cycle after that it will select value from y.SO how can i write code for this procedure.One more thing is that i will use this processing element latter in my architecture.it is one part of my architecture
 

verilog code(urgent)

You can use a 16 bit shift register. Feed a pulse into the input, then sixteen clocks later it appears at the output.
 

Re: verilog code(urgent)

here is one example how you can do that!

Code: 
module cntrl(/*AUTOARG*/
   // Outputs
   mux_sel, 
   // Inputs
   clk, reset_n
   );
   input clk, reset_n;
   output      mux_sel;
   reg [4:0]   control;

   assign      mux_sel = &control;

   always @(posedge clk or negedge reset_n)
     if (!reset_n)
       control <= 0;
     else
       control <= control + 1'b1;
endmodule // cntrl
 

verilog code(urgent)

I agree with nand_gates
,maybe a counter is better!!
 

verilog code(urgent)

A counter would be smaller.
A shift register would support multi-pulse pipelining.
We don't know which feature is more important to the project.
 

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