Measuring INL and DNL performance and SFDR of DAC

Dear all,
If I have 500MHz DAC,my INL and DNL are lower l 1LSB.When I measure SFDR,
how much signal frequency and clk frequency are suitable to the project?
For example,if my analog signal is 1MHz, how do I do for my inputs?
Because my inputs may be not regulate, how do I do for my input in hspice?
Thanks.

Re: DAC & SFDR

Hi yen,

Can you tell me to measure INL and DNL method of DAC on HSPICE tools?

I'm design the Cruuent-steering DAC, but, I'm not understanding to measure INL and DNL performance.

Thank you very much!

DAC & SFDR

refer to :

Re: DAC & SFDR

yen said:

Dear all,
If I have 500MHz DAC,my INL and DNL are lower l 1LSB.When I measure SFDR,
how much signal frequency and clk frequency are suitable to the project?
For example,if my analog signal is 1MHz, how do I do for my inputs?
Because my inputs may be not regulate, how do I do for my input in hspice?
Thanks.

Click to expand...

My DAC is 12 bits.

Added after 1 minutes:

neter said:

Hi yen,

Can you tell me to measure INL and DNL method of DAC on HSPICE tools?

I'm design the Cruuent-steering DAC, but, I'm not understanding to measure INL and DNL performance.

Thank you very much!

Click to expand...

Dear neter,
Your inputs are square waves.You can mearsure INL and DNL.

Re: DAC & SFDR

Dear yen,

My DAC is 8bits.

Can you provide input test square waves picture to give me reference ?

Thank you very much.

Re: DAC & SFDR

neter said:

Dear yen,

My DAC is 8bits.

Can you provide input test square waves picture to give me reference ?

Thank you very much.

Click to expand...

Like this

VV0 A0 0 pulse (1.8V 0V 0n 0.1n 0.1n 2n 4n)
VV1 A1 0 pulse (1.8V 0V 0n 0.1n 0.1n 4n 8n)
VV2 A2 0 pulse (1.8V 0V 0n 0.1n 0.1n 8n 16n)
VV3 A3 0 pulse (1.8V 0V 0n 0.1n 0.1n 16n 32n)

VV4 A4 0 pulse (1.8V 0V 0n 0.1n 0.1n 32n 64n)
VV5 A5 0 pulse (1.8V 0V 0n 0.1n 0.1n 64n 128n)
VV6 A6 0 pulse (1.8V 0V 0n 0.1n 0.1n 128n 256n)
VV7 A7 0 pulse (1.8V 0V 0n 0.1n 0.1n 256n 512n)
VV8 A8 0 pulse (1.8V 0V 0n 0.1n 0.1n 512n 1024n)
VV9 A9 0 pulse (1.8V 0V 0n 0.1n 0.1n 1024n 2048n)
VV10 A10 0 pulse (1.8V 0V 0n 0.1n 0.1n 2048n 4096n)
VV11 A11 0 pulse (1.8V 0V 0n 0.1n 0.1n 4096n 8192n)
VV14 CLK 0 pulse (0V 1.8V 0n 0.1n 0.1n 1n 2n)

Added after 2 minutes:

sunking said:

refer to :
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Click to expand...

I know how to simulate SFDR of dac.But I don't how to generate my inputs that my output is like sine wave. How do I do? Thanks.

Re: DAC & SFDR

There are some solutions.
1. Using matlab to generate the digital sine wave.
2. Using verilog-A to write a ideal ADC, and then generate digital sine wave. In this case, you should use some simulator like spectre.

Re: DAC & SFDR

nathanee said:

There are some solutions.
1. Using matlab to generate the digital sine wave.
2. Using verilog-A to write a ideal ADC, and then generate digital sine wave. In this case, you should use some simulator like spectre.

Click to expand...

Dear nathanee,
I use 1.But matlab's signal is 0 or 1.They are not regular.(I use hspice to simulate). How do I type my inputs? If I select 2, how do I do?
Can you tell me in detail? Maybe you can take a example. Thanks.

Re: DAC & SFDR

I think the DNL and INL is the mismatch about the device.

So the DNL and INL would have to be tested after the chip is fabricated.

But you can get the DNL and INL with the behavior model in the Hspice

environment. In pracitce, the behavior model is setted up by matble with the

mismatch model about process.

Re: DAC & SFDR

nathanee said:

There are some solutions.
1. Using matlab to generate the digital sine wave.
2. Using verilog-A to write a ideal ADC, and then generate digital sine wave. In this case, you should use some simulator like spectre.

Click to expand...

I am interesed about SFDR.
Maybe you can write ideal ADC in hspice.
But it is not easy.
I think ideal DAC is easy.
I see tsmc 0.18µ. It has a 8 bits ADC.
But not 12 bits.
I also interest 1 and 2.
Can you tell me detail?
Thanks.

Re: DAC & SFDR

At the output you can use an ideal verilog A coded low pass filter of with cutoff say 0.6Fs, then the reconstructed wave you can use for plotting sfdr.
In actual measurement also, spectrum analysers have a band pass filter in the frontend so adding a lpf is analogus to real measurment.

Re: DAC & SFDR

yen said:

Like this

VV0 A0 0 pulse (1.8V 0V 0n 0.1n 0.1n 2n 4n)
VV1 A1 0 pulse (1.8V 0V 0n 0.1n 0.1n 4n 8n)
VV2 A2 0 pulse (1.8V 0V 0n 0.1n 0.1n 8n 16n)
VV3 A3 0 pulse (1.8V 0V 0n 0.1n 0.1n 16n 32n)

VV4 A4 0 pulse (1.8V 0V 0n 0.1n 0.1n 32n 64n)
VV5 A5 0 pulse (1.8V 0V 0n 0.1n 0.1n 64n 128n)
VV6 A6 0 pulse (1.8V 0V 0n 0.1n 0.1n 128n 256n)
VV7 A7 0 pulse (1.8V 0V 0n 0.1n 0.1n 256n 512n)
VV8 A8 0 pulse (1.8V 0V 0n 0.1n 0.1n 512n 1024n)
VV9 A9 0 pulse (1.8V 0V 0n 0.1n 0.1n 1024n 2048n)
VV10 A10 0 pulse (1.8V 0V 0n 0.1n 0.1n 2048n 4096n)
VV11 A11 0 pulse (1.8V 0V 0n 0.1n 0.1n 4096n 8192n)
VV14 CLK 0 pulse (0V 1.8V 0n 0.1n 0.1n 1n 2n)

Added after 2 minutes:



I know how to simulate SFDR of dac.But I don't how to generate my inputs that my output is like sine wave. How do I do? Thanks.

Click to expand...

Hi yen,
VV0 to VV11 is the input pulse of 12 bits DAC right? VV14 is for CLK but where is the CLK in the DAC schematic, for ex. R-2R ladder. Thanks.