why we are going for functional verification

can any one tell me about the difference between functional verificatiopn .formal verification and assertion based verification..and what are the tools used for it.

Functional Verification is the process of verifying that a design operates correctly as described in the architectural and functional specifications. It targets the logical design of the product, and typically assumes that the physical design process is unrelated.

In assertion-based verification, RTL assertions are used to capture design intent in a verifiable form as the design is created, providing portable monitors that check for correct behavior. During simulation, assertions improve observability coverage, making the source of an error evident. Simulation debug time is greatly reduced. As targets for formal verification, assertions improve controllability coverage.

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i tot there is 2 types for this aspect... functional verification and timing verification...

functional verification is just to check the whether the output is as expected wthout consider the timing issue

timing verification involve everything...

correct?

regards,
sp

Hi.

Formal verification can be viewed from two points of view: one is model checking and the other is equivalence checking. Model checking is to check the equivalence between the specification and the design. Equivalence checking is to check the original design and the transformed design. Here, the examples of the transformed design are synthesized design, back-annotated design, etc., that is obtained from the original design, say, VHDL or Verilog HDL design.

By the way, the objective of the functional simulation is checking the logic of the design from the functionality point of view. The functional simulation is very important in the design flow in case of some debugging required.

so is functional verification and formal verificationa are same ..

what are the tools used for different verifications.