Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The first , you have to find out the power comsumption of the memory you use in your design.
The second, you have to know the current and metal width ratio.
Then you will understand how width of metal you need.
thank nemolee!
As you said, I can read power consumption in data sheet generated by mem compiler and current density in per metal layer.
But there are some connection from power strap and mesh to mem's power ring, the assumption is rational that current in per connection point devided by 2 ?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.