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  1. #1
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    SRAM RC Extraction Simulation Does NOT Match Schematic Simulation

    Hi, really hope someone could help me.

    About the circuit" I am doing an in-memory calculation structure very similar to SRAM which has both write and read.
    The writing process writes data into the structure; the reading process needs some inputs and will do some performance with the stored data inside the structure then generates some outputs.

    Problems: The simulation of the schematic netlist works well; however, after layout and RC extraction, it does not work properly. I use Cadence Virtuoso with Calibre PEX to do the RC extraction.
    The problems typically happen when the RC extraction contains R values (eg. R+C+CC or R+C), the stored value in the cell becomes unstable and might flip its value (eg. In the reading process, previously-stored 0 inside the cell in the writing process jitters and end up with 1). And of course, the output is also wrong. Ideally, the stored value should not change during the reading process.
    If I do RC extraction without R (C+CC), the output is always correct, the stored values maintain the values, just like what I got from the schematic netlist simulation.

    Initially, I thought this might because the resistances are too large. But I did not get any luck after increase the metal width as wide as possible.
    Later I noticed that in the tech documentation, it mentions if the oxide is too long when carrying signals, the signals might not be stable. So I cut those suspect long oxide into small pieces.
    Unfortunately, after trying both of these, the RC extraction circuit still shows a very similar wrong behavior. The output is wrong. The jitters on the stored value get smoother but the stored value still cannot hold itself.

    Could anyone give me some suggestions about what I should do next? Any debug mechanism I could possibly use? Anyone had a similar problem before and got it solved?
    Thank you very much.

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  2. #2
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    Re: SRAM RC Extraction Simulation Does NOT Match Schematic Simulation

    Quote Originally Posted by EEPuppyPuppy View Post
    structure very similar to SRAM which has both write and read
    Static ram? This can be made with RS flip-flops. It's extremely stable. Holds a state indefinitely without any refresh. There should be no instability caused by reading its state.

    However your description sounds like dynamic ram (DRAM). Bits are stored as a charge on a capacitor. Its voltage is applied to bias a mosfet. The mosfet output is read rather than reading the capacitor directly.
    The capacitors tend to lose charge quickly therefore DRAM needs a frequent refresh routine. This is done by reading a capacitor, then writing the value back to it.



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  3. #3
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    Re: SRAM RC Extraction Simulation Does NOT Match Schematic Simulation

    Quote Originally Posted by BradtheRad View Post
    Static ram? This can be made with RS flip-flops. It's extremely stable. Holds a state indefinitely without any refresh. There should be no instability caused by reading its state.

    However your description sounds like dynamic ram (DRAM). Bits are stored as a charge on a capacitor. Its voltage is applied to bias a mosfet. The mosfet output is read rather than reading the capacitor directly.
    The capacitors tend to lose charge quickly therefore DRAM needs a frequent refresh routine. This is done by reading a capacitor, then writing the value back to it.
    Hi, really appreciate your response.
    The structure is more close to a SRAM, so the bits are not stored as charge on a capacitor but within a couple-of-inverter loop.
    I am going to check each parasitic resistance and see which ones are the problems. I guess if I do not get any luck with that I will check the SR Flip-flop to replace part of my structure.



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    Re: SRAM RC Extraction Simulation Does NOT Match Schematic Simulation

    Quote Originally Posted by EEPuppyPuppy View Post
    the bits are not stored as charge on a capacitor but within a couple-of-inverter loop
    Is this your approach? Very clever. It's similar to a pulse generator made from 2 invert-gates with the addition of a capacitor and resistor.
    To make it into a memory cell doesn't need the capacitor, simply a bit of hysteresis using a resistor.

    Click image for larger version. 

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    By puling the input high or low momentarily, it forces the output to that state, holding it indefinitely.
    This strategy could be simpler to operate, as compared to a conventional RS flip flop.



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    Re: SRAM RC Extraction Simulation

    Hi,

    It's like a bus keeper circuit.
    It holds the last state of the (input) line.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.


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    Re: SRAM RC Extraction Simulation

    The problem of a large difference between post-layout circuit simulation and schematic simulation is a very common one.

    The usual process to debug this is to find out what parasitic elements are the most critical, in destroying your nice (schematic) circuit behavior.
    I would suggest to do R-only extraction, and see if your circuit behaves well, or not.

    Next, try to imagine, to envision (or to simulate) what would be a potential impact of various parasitics on your circuit misbehavior - such as IR drop on bias lines, or large delay, or mismatch between nets, etc.
    You can insert presistor and pcapacitor elements into your schematic, with values corresponding to extracted parasitics, and see what happens, which of them deteriorates your circuit behavior.

    Things to look at, are port to device or device to device effective (parasitic resistance), RC delay, coupling between nets, mismatch (capacitive or resistive) in your sense amplifier, etc.

    In general, for slow / low performance circuits, and in older technology nodes, parasitics is usually a smaller problem, and becomes much more important for advanced nodes (let's say 20nm and below), and/or for high-speed circuits.



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  7. #7
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    Re: SRAM RC Extraction Simulation

    Are you using the bitcell provided by the foundry? Otherwise you won't get a nice SRAM behavior because of missing SRAM-specific layers in the layout. Extraction and spice models become very different beasts when they encounter the correct layers.
    Really, I am not Sam.



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    Re: SRAM RC Extraction Simulation

    I would do a only-R extraction and follow the signal node by node to identify which R is causing the problem. As ThisIsNotSam mentioned, the problem might be due to an extraction error, a non realistic R value or a wrong node connection .. SRAMs are always touchy. That is why checking the R-Network node by node is the most efficient way to debug.



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