noureddine-as
Junior Member level 2
SDF file backannotation problem: "Instance X does not have a generic named Y"
After synthesizing a SystemVerilog IP in Design Compiler 2019, I exported the SDF timing backannotation file to be used in VSIM for post-synthesis simulation.
However, VSIM outputs a lots of errors like this
Knowing that in the generated Gate netlist I get the following
Now, when I check the generic parameters of the Entity "XNR21" in the VITAL library I found the following definition.
Which confirms that, indeed the entity doesn't have those "*_posedge" and "*_negedge" generics. Any ideas how to resolve this problem ?
After synthesizing a SystemVerilog IP in Design Compiler 2019, I exported the SDF timing backannotation file to be used in VSIM for post-synthesis simulation.
However, VSIM outputs a lots of errors like this
Code:
# ** Error (suppressible): (vsim-SDF-3240) ......./SDF_FILE.sdf(64557): Instance '/tb/ip_instance/ip_top/U25942' does not have a generic named 'tpd_a_q_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) ......./SDF_FILE.sdf(64557): Instance '/tb/ip_instance/ip_top/U25942' does not have a generic named 'tpd_a_q_negedge'.
# ** Error (suppressible): (vsim-SDF-3240) ......./SDF_FILE.sdf(64557): Instance '/tb/ip_instance/ip_top/U25942' does not have a generic named 'tpd_b_q_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) ......./SDF_FILE.sdf(64557): Instance '/tb/ip_instance/ip_top//U25942' does not have a generic named 'tpd_b_q_negedge'.
Knowing that in the generated Gate netlist I get the following
Code:
XNR21 U25942 ( .A(n20301), .B(n20300), .Q(n20320) );
Now, when I check the generic parameters of the Entity "XNR21" in the VITAL library I found the following definition.
Which confirms that, indeed the entity doesn't have those "*_posedge" and "*_negedge" generics. Any ideas how to resolve this problem ?
Code:
-- entity declaration --
entity XNR21 is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := True;
tpd_A_Q : VitalDelayType01 := (1 ps, 1 ps);
tpd_B_Q : VitalDelayType01 := (1 ps, 1 ps);
tipd_A : VitalDelayType01 := (0 ps, 0 ps);
tipd_B : VitalDelayType01 := (0 ps, 0 ps));
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
attribute VITAL_LEVEL0 of XNR21 : entity is TRUE;
end XNR21;