riti
Member level 1
Hello,
I am new user in writing UPF for my design. I am starting with very basic stuff and i don't have accessibility to make changes big changes in RTL code. Please look into my below mentioned script and tell me if any changes required? or i can used directly in Design compiler.
a) Do i need changes in tech , lib files also ?
b) Also i need to define these ports in RTL (VSS, TOP_VDD1) or directly i can give in synthesis ?
I am new user in writing UPF for my design. I am starting with very basic stuff and i don't have accessibility to make changes big changes in RTL code. Please look into my below mentioned script and tell me if any changes required? or i can used directly in Design compiler.
a) Do i need changes in tech , lib files also ?
b) Also i need to define these ports in RTL (VSS, TOP_VDD1) or directly i can give in synthesis ?
Code dot - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 set upf_create_implicit_supply_sets false create_power_domain TOP -include_scope create_supply_net TOP_VDD1 -domain TOP create_supply_net VSS -domain TOP set_domain_supply_net TOP -primary_power_net TOP_VDD1 -primary_ground_net VSS create_supply_port VSS -domain TOP -direction in create_supply_port TOP_VDD1 -domain TOP -direction in add_port_state VSS -state {state1 0.000000} add_port_state TOP_VDD1 -state {state1 1.080000} connect_supply_net VSS -ports VSS connect_supply_net TOP_VDD1 -ports TOP_VDD1 set_voltage 1.08 -object_list { TOP_VDD1 } set_voltage 0 -object_list { VSS } set_operating_conditions WCCOM compile_ultra write -pg -hierarchy -format verilog -output file_synth.v
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