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7th March 2020, 15:29 #1
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7th March 2020, 15:36 #2
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Re: Class ab amplifier dc biasing
Obviously, the statement is not true, except for Vout = 0. Then the answer is trivial.

7th March 2020, 15:57 #3
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7th March 2020, 16:09 #4
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Re: Class ab amplifier dc biasing
Vs = 0 doesn't strictly cause Vout = 0. R1, R2, Q1, Q2 can have different parameters.
You should know if labels "+VCC" and "VCC" implicate voltage levels of +/ VCC, I just guessed so. But if you ask me if it's true...
To make it clear in circuit analysis terms, you would sketch voltage sources. Seriously, I don't understand what's exactly the objective of your question if it involves simplifications and inaccuracies.

8th March 2020, 05:04 #5
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Re: Class ab amplifier dc biasing
for that to be true the xtors must be very close in gain ...

8th March 2020, 19:51 #6
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8th March 2020, 22:05 #7
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Re: Class ab amplifier dc biasing
The output KVL applies to Vcc, Vce(Q2), Vce(Q1), + Vcc. We have:
Vcc+Vce(Q2)+VC(Q1) = Vcc that is:
Vce(Q1)+Vce(Q2) = 2Vcc
if Vout = 0 we have (set Vout=0 and apply KVL to both lower and upper transistors):
Vcc+Vce(Q2) = 0 ==> Vce(Q2) = Vcc
and Vce(Q1) = Vcc
This condition can be reached when Vs=0 if the npn and pnp behave exactly the same (as already said by FvM). Under this condition, if Vs <> 0 then
Vce(Q1) <> Vce(Q2) and of course Vce(Q1)+Vce(Q2) = 2Vcc applies.
This means the output voltage can span from Vcc+Vce(Q2sat) to +VccVce(Q1sat)
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9th March 2020, 10:09 #8
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