# Class ab amplifier dc biasing

1. ## Class ab amplifier dc biasing

Hi can you tell me what KVL loop in the circuit should I use to prove that VCE1 = VCE2 = VCC voltage. Thanks.

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2. ## Re: Class ab amplifier dc biasing

Obviously, the statement is not true, except for Vout = 0. Then the answer is trivial.

3. ## Re: Class ab amplifier dc biasing

Originally Posted by FvM
Obviously, the statement is not true, except for Vout = 0. Then the answer is trivial.
I forgot to mention that Vs is ignored. Can you tell me that trivial answer? Do we just say that it's equal VCC becuase it's labled VCC?

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4. ## Re: Class ab amplifier dc biasing

Vs = 0 doesn't strictly cause Vout = 0. R1, R2, Q1, Q2 can have different parameters.

You should know if labels "+VCC" and "-VCC" implicate voltage levels of +/- VCC, I just guessed so. But if you ask me if it's true...

To make it clear in circuit analysis terms, you would sketch voltage sources. Seriously, I don't understand what's exactly the objective of your question if it involves simplifications and inaccuracies.

5. ## Re: Class ab amplifier dc biasing

for that to be true the xtors must be very close in gain ...

6. ## Re: Class ab amplifier dc biasing

Originally Posted by Easy peasy
for that to be true the xtors must be very close in gain ...
Hi. How is the voltage affected by the gain of the transistors?

7. ## Re: Class ab amplifier dc biasing

The output KVL applies to -Vcc, Vce(Q2), Vce(Q1), + Vcc. We have:

-Vcc+Vce(Q2)+VC(Q1) = Vcc that is:
Vce(Q1)+Vce(Q2) = 2Vcc

if Vout = 0 we have (set Vout=0 and apply KVL to both lower and upper transistors):

-Vcc+Vce(Q2) = 0 ==> Vce(Q2) = Vcc
and Vce(Q1) = Vcc

This condition can be reached when Vs=0 if the npn and pnp behave exactly the same (as already said by FvM). Under this condition, if Vs <> 0 then
Vce(Q1) <> Vce(Q2) and of course Vce(Q1)+Vce(Q2) = 2Vcc applies.

This means the output voltage can span from -Vcc+Vce(Q2sat) to +Vcc-Vce(Q1sat)

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8. ## Re: Class ab amplifier dc biasing

Originally Posted by albbg
The output KVL applies to -Vcc, Vce(Q2), Vce(Q1), + Vcc. We have:

-Vcc+Vce(Q2)+VC(Q1) = Vcc that is:
Vce(Q1)+Vce(Q2) = 2Vcc

if Vout = 0 we have (set Vout=0 and apply KVL to both lower and upper transistors):

-Vcc+Vce(Q2) = 0 ==> Vce(Q2) = Vcc
and Vce(Q1) = Vcc

This condition can be reached when Vs=0 if the npn and pnp behave exactly the same (as already said by FvM). Under this condition, if Vs <> 0 then
Vce(Q1) <> Vce(Q2) and of course Vce(Q1)+Vce(Q2) = 2Vcc applies.

This means the output voltage can span from -Vcc+Vce(Q2sat) to +Vcc-Vce(Q1sat)
Hi. albg, thank you! This is the answer i was looking for!

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