+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Newbie level 3
    Points: 65, Level: 1

    Join Date
    Nov 2019
    Posts
    4
    Helped
    0 / 0
    Points
    65
    Level
    1

    FIR Filter general question

    Dea Forum

    Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point.

    Now, I want to implement this FIR in my FPGA ,with buil in 18x18 multiplier.

    So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling the bigger coefficient such that arrive < than 2^17 , and cutting the decimal.
    That means, all coefficient preserve the precision more than possible when multiplied for a big number.

    First question are:
    1)I read this operation introduce a DC offset.Why ?
    2)Why DC offset is a so big disturbing problem


    Please check if next considerations are correct:

    Image the input signal comes from a AD of 16 bit for example..When arrive the input signal, every multiplication sure will produce in the worst case 16+18=34 bit.
    Last adder must be the more problematic, because (in worst case) will trasport the 34bit info multiplied for N coefficient .
    Exsample...If I have 100 Coefficients,the last adders must work with value like (2^34) *100 -->need 8 bit more .
    If I have not this bit, input signal must be scaled

    So,question 3) is correct the worst case consideraton?
    IN base to what I limit my signal input (some test ????)

    Thanks very much and excuse for long message

    Roberto

    •   AltAdvertisement

        
       

  2. #2
    Super Moderator
    Points: 81,122, Level: 69
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    16,453
    Helped
    3734 / 3734
    Points
    81,122
    Level
    69

    Re: FIR Filter general question

    Hi.

    The FIR should not create DC.
    But for sure the values are multiplied wit 2^17, thus the output signal will be multiplied with the same factor ... the input DC, too.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



    •   AltAdvertisement

        
       

  3. #3
    Super Moderator
    Points: 264,250, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    46,176
    Helped
    14043 / 14043
    Points
    264,250
    Level
    100

    Re: FIR Filter general question

    So, I transform the coefficient in integer value of max 17 bit (1 bit for sign)
    Why not simply treat the signal as 18 bit signed? If your original ADC signal is 16 bit, you'll use 16 rather than 18 bit signed. Similarly, the coefficient resolution will be demanded by the filter transfer function accuracy, not the multiplier width. A higher coefficient resolution than 16 bit is rarely significant. You can check the effect of coefficient rounding either in Matlab or in FPGA tools like Quartus FIR compiler.

    I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point.
    It get can be useful to scale the coefficient with a factor so that the sum of coefficients is a power of two. In this case you can easily scale the filter output to unity DC gain by shifting the result.

    Image the input signal comes from a AD of 16 bit for example..When arrive the input signal, every multiplication sure will produce in the worst case 16+18=34 bit.
    Last adder must be the more problematic, because (in worst case) will transport the 34bit info multiplied for N coefficient .
    Exsample...If I have 100 Coefficients,the last adders must work with value like (2^34) *100 -->need 8 bit more .
    If I have not this bit, input signal must be scaled
    Depending on the filter bandwidth, significant filter output for 16 bit ADC can be expected somewhere between 16 and 24 bits, rarely more. Respectively you rather drop less signifikant output bits than scaling the input. Typically, a first bit reduction will occur after the multiplier, the second after the final addition. Filter design tools will suggest reasonable settings depending on the output width and filter order. In case of doubt, a simulation shows which bits are significant.



    •   AltAdvertisement

        
       

  4. #4
    Newbie level 3
    Points: 65, Level: 1

    Join Date
    Nov 2019
    Posts
    4
    Helped
    0 / 0
    Points
    65
    Level
    1

    Re: FIR Filter general question

    Thanks very much for all the reply to my long question.

    1)Is clear now that, the DC component is the sum of <hi> coefficient . So,if I have some DC offset at input, it will produce a DC out very large (DC_out= DC_offs * sum(hi) ).

    Questio is: I cant find a rules for create coeffincient at sum=0 for DC block.
    Also Matlab dont give such coefficient

    Or could be better to insert a DC block at input.

    2)About FvM reply:
    You say that, for have DC gain =1 ,we divide the out for sum of coeff: if this sum is a power of 2, shifting wil be a very efficient way to divide.

    But cant find a rules for get this coefficient that sum is power 2, apart looking 1 to 1 coefficient, and do with hand.

    Thanks very much
    Roberto



  5. #5
    Newbie level 4
    Points: 137, Level: 1

    Join Date
    Aug 2019
    Posts
    6
    Helped
    2 / 2
    Points
    137
    Level
    1

    Re: FIR Filter general question

    To get sum of coeffs as power of 2:

    coeffs = round(2^n *coeffs/sum(coeffs));

    proper low pass filter will not generate dc but may be you mean truncation within any computation, yes



    •   AltAdvertisement

        
       

  6. #6
    Super Moderator
    Points: 264,250, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    46,176
    Helped
    14043 / 14043
    Points
    264,250
    Level
    100

    Re: FIR Filter general question

    proper low pass filter will not generate dc but may be you mean truncation within any computation
    DC gain of the low pass filter is just a synonym of pass band gain. Of course there should be no DC offset generated, apart from very small rounding errors.

    I'm focussing on DC gain because it can be most easily calculated. If you have other filters than low pass, coefficient scaling must be calculated differently.

    coeffs = round(2^n *coeffs/sum(coeffs));
    Yes, you can do this calculation in your Matlab script.



--[[ ]]--