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15th January 2020, 20:45 #1
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FIR Filter general question
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Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point.
Now, I want to implement this FIR in my FPGA ,with buil in 18x18 multiplier.
So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling the bigger coefficient such that arrive < than 2^17 , and cutting the decimal.
That means, all coefficient preserve the precision more than possible when multiplied for a big number.
First question are:
1)I read this operation introduce a DC offset.Why ?
2)Why DC offset is a so big disturbing problem
Please check if next considerations are correct:
Image the input signal comes from a AD of 16 bit for example..When arrive the input signal, every multiplication sure will produce in the worst case 16+18=34 bit.
Last adder must be the more problematic, because (in worst case) will trasport the 34bit info multiplied for N coefficient .
Exsample...If I have 100 Coefficients,the last adders must work with value like (2^34) *100 >need 8 bit more .
If I have not this bit, input signal must be scaled
So,question 3) is correct the worst case consideraton?
IN base to what I limit my signal input (some test ????)
Thanks very much and excuse for long message
Roberto

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15th January 2020, 23:40 #2
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Re: FIR Filter general question
Hi.
The FIR should not create DC.
But for sure the values are multiplied wit 2^17, thus the output signal will be multiplied with the same factor ... the input DC, too.
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

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16th January 2020, 09:10 #3
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Re: FIR Filter general question
So, I transform the coefficient in integer value of max 17 bit (1 bit for sign)
I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point.
Image the input signal comes from a AD of 16 bit for example..When arrive the input signal, every multiplication sure will produce in the worst case 16+18=34 bit.
Last adder must be the more problematic, because (in worst case) will transport the 34bit info multiplied for N coefficient .
Exsample...If I have 100 Coefficients,the last adders must work with value like (2^34) *100 >need 8 bit more .
If I have not this bit, input signal must be scaled

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16th January 2020, 13:51 #4
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Re: FIR Filter general question
Thanks very much for all the reply to my long question.
1)Is clear now that, the DC component is the sum of <hi> coefficient . So,if I have some DC offset at input, it will produce a DC out very large (DC_out= DC_offs * sum(hi) ).
Questio is: I cant find a rules for create coeffincient at sum=0 for DC block.
Also Matlab dont give such coefficient
Or could be better to insert a DC block at input.
2)About FvM reply:
You say that, for have DC gain =1 ,we divide the out for sum of coeff: if this sum is a power of 2, shifting wil be a very efficient way to divide.
But cant find a rules for get this coefficient that sum is power 2, apart looking 1 to 1 coefficient, and do with hand.
Thanks very much
Roberto

16th January 2020, 14:49 #5
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Re: FIR Filter general question
To get sum of coeffs as power of 2:
coeffs = round(2^n *coeffs/sum(coeffs));
proper low pass filter will not generate dc but may be you mean truncation within any computation, yes

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16th January 2020, 15:24 #6
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Re: FIR Filter general question
proper low pass filter will not generate dc but may be you mean truncation within any computation
I'm focussing on DC gain because it can be most easily calculated. If you have other filters than low pass, coefficient scaling must be calculated differently.
coeffs = round(2^n *coeffs/sum(coeffs));
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