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daskk62
Guest
I made a verilog code for an up counter. I synthesized it in cadence genus tool by setting the clock frequency 30 MHz. After that I made a layout in Cadence Innovus tool for the same. Now my question is, how to find at what frequency my up counter ASIC will work? In FPGA the same verilog code was working at a clock rate of 20 MHz.