big_fudge98
Member level 2
Hi all,
I have recently done layouts of some analog blocks such as op-amps, current source etc. Upon getting them reviewed by an experienced individual from the industry, I recieved the following comments:
1) Do not share source/drain terminals and instead use multipliers.
2) Do not share dummy transistor source/drain. Instead keep minimum spacing between dummies and design transistors. Short dummies to VSS/VDD (NMOS?PMOS).
Unfortunately, I could not ask him the reason for his comment. Does anyone know why?
Thanks.
I have recently done layouts of some analog blocks such as op-amps, current source etc. Upon getting them reviewed by an experienced individual from the industry, I recieved the following comments:
1) Do not share source/drain terminals and instead use multipliers.
2) Do not share dummy transistor source/drain. Instead keep minimum spacing between dummies and design transistors. Short dummies to VSS/VDD (NMOS?PMOS).
Unfortunately, I could not ask him the reason for his comment. Does anyone know why?
Thanks.