Pastel
Member level 3
Hello!
There is something a little bit unclear to me.
When I started programming a few months ago, I made a generator for arbitrary
signals. In order to check how it works, I have loaded a sine wave and the
generator just addresses the array and sets the address to a DAC.
At one point, it stopped working, I had a really weird output. After some
search on the web, I found out that the timing might not be optimal, so I
learned how to set time constraints, which fixed the problem. Basically,
the distance between data vs clock of the DAC I use are important, and
this makes constraints between system clock and DAC clock.
Now I have tried something else on a copy of the original project. I didn't set any time
constraints, but the PLL I use allows me to accurately set the phase between
one signal and the master clock. This method also fixes the problem, and depending
on the phase I set, the output might be nice or completely screwed up.
NB: In my application, I generate sys_clk and dac_clk from the physical input clk.
Both are generated by the same PLL, I can be sure of their relationship (phase),
and I verified it on the scope.
As PLLs allow me to build any kind of signal with any phase, I can tune the distance
between the edges of the DAC, so this method also seems valid to me. Is this a good
method to set time constraints? What would be the drawbacks of this method?
Thanks for any hint.
Pastel
There is something a little bit unclear to me.
When I started programming a few months ago, I made a generator for arbitrary
signals. In order to check how it works, I have loaded a sine wave and the
generator just addresses the array and sets the address to a DAC.
At one point, it stopped working, I had a really weird output. After some
search on the web, I found out that the timing might not be optimal, so I
learned how to set time constraints, which fixed the problem. Basically,
the distance between data vs clock of the DAC I use are important, and
this makes constraints between system clock and DAC clock.
Now I have tried something else on a copy of the original project. I didn't set any time
constraints, but the PLL I use allows me to accurately set the phase between
one signal and the master clock. This method also fixes the problem, and depending
on the phase I set, the output might be nice or completely screwed up.
NB: In my application, I generate sys_clk and dac_clk from the physical input clk.
Both are generated by the same PLL, I can be sure of their relationship (phase),
and I verified it on the scope.
As PLLs allow me to build any kind of signal with any phase, I can tune the distance
between the edges of the DAC, so this method also seems valid to me. Is this a good
method to set time constraints? What would be the drawbacks of this method?
Thanks for any hint.
Pastel