ibtesam90
Newbie level 6
I am designing a very basic gate (inverter) in custom designer using SAED PDK90nm. I am able to create the schematics and layouts and generate Parasitics. When I run the simulation on testbench circuit (using schematic only) it works fine, however, when I run the same testbench with parasitics it does not work. It gives warning and Extra terminal VDD and VSS found in symbol not found in starrc.
I am attaching the waveforms for both the simulations. The top 4 are for the schematic and it does not show the vss option. however in post-LPE the vss has the same waveform as input.
net5: VDD
net7: Input signal
out : output signal
0: ground
i haven't defined any net as VSS in test bench circuit.
I have spent two days to figure out what is the problem but unable to find on internet.
I am attaching the waveforms for both the simulations. The top 4 are for the schematic and it does not show the vss option. however in post-LPE the vss has the same waveform as input.
net5: VDD
net7: Input signal
out : output signal
0: ground
i haven't defined any net as VSS in test bench circuit.
I have spent two days to figure out what is the problem but unable to find on internet.