buenos
Advanced Member level 3
- Joined
- Oct 24, 2005
- Messages
- 960
- Helped
- 40
- Reputation
- 82
- Reaction score
- 24
- Trophy points
- 1,298
- Location
- Florida, USA
- Activity points
- 9,116
What's the difference between TRN and AXI4-Stream interfaces?
I implemented a PCI-express transaction layer logic that worked on the Spartan-6 device. The PCIe endpoint IP had a TRN interface that simply passed the TLP packet to the user logic, my user logic that decoded the TLPs for generating local wishbone bus transactions.
Now I want to make the same thing on Kintex Ultrascale device, but its PCIE-EP IP has an AXI4-Streaming interface instead of TRN. It seems a lot more complicated. The specs show that the axi stream has a "descriptor" headers with all kinds of data like address and so on. But if a complete TLP is pased to user logic, while the PCIe standard TLP also has most of those fileds.
Question: The Ultrascale PCIe IP Axi bus descriptor is redundant with the TLP header, or the TLP passed to my user logic is incomplete? What should I do with descriptor header, can I just ignore it?
Anyone experience with this?
I implemented a PCI-express transaction layer logic that worked on the Spartan-6 device. The PCIe endpoint IP had a TRN interface that simply passed the TLP packet to the user logic, my user logic that decoded the TLPs for generating local wishbone bus transactions.
Now I want to make the same thing on Kintex Ultrascale device, but its PCIE-EP IP has an AXI4-Streaming interface instead of TRN. It seems a lot more complicated. The specs show that the axi stream has a "descriptor" headers with all kinds of data like address and so on. But if a complete TLP is pased to user logic, while the PCIe standard TLP also has most of those fileds.
Question: The Ultrascale PCIe IP Axi bus descriptor is redundant with the TLP header, or the TLP passed to my user logic is incomplete? What should I do with descriptor header, can I just ignore it?
Anyone experience with this?