RTYPRABHAKAR
Newbie level 3
VERILOG CODE to generate clock signal for 10Mhz with system clock 50Mhz
Need Verilog code for generating two signals
1.clock signal to generate 10Mhz
2. at the same time the second signal has to toggle its sate on specific count on "negative" edge period
3. How to call a function after a specific clock period?
here i'm sharing a clock signal generation verilog code of 10Mhz from system clock 50Mhz
Need Verilog code for generating two signals
1.clock signal to generate 10Mhz
2. at the same time the second signal has to toggle its sate on specific count on "negative" edge period
3. How to call a function after a specific clock period?
here i'm sharing a clock signal generation verilog code of 10Mhz from system clock 50Mhz
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module clk_div(clk,reset, clk_out ); parameter N=5; parameter R=3;// Detramains number of binary bits to present the value of "N" input clk; input reset; output clk_out; reg [R-1:0] pos_count, neg_count; wire [R-1:0] r_nxt; always @(posedge clk) if (reset) pos_count <=0; else if (pos_count ==(N-1)) pos_count <=0; else pos_count<= pos_count +1; always @(negedge clk) if (reset) neg_count <=0; else if (neg_count ==(N-1)) neg_count <=0; else neg_count<= neg_count +1; assign clk_out = ((pos_count == (N-1)) | (neg_count == (N-1))); endmodule
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