arkadyy
Newbie level 4
Hello,
For the first time I deal with crossing clock domains (slow-to-fast) and I have faced a problem.
I recieve constant stream of data, which I have to filter, but before processing data have to move from 100 MHz to 240 MHz domain. I used standard asynchronous FIFO approach and I manage to succesfully partition my data and transfer to new domain. Effects are visiable on attached screen shot. The problem is that when I feed that partitioned data into Xilinx FIR Compiler, my outputs signal turns into garbage.
So, my question is how to merge, partitioned by CDC data to obtain stream like before clock conversion? Maybe there are some methods to do so, which I'm not aware of, I will be glad to learn some new techniques and gain more knowledge. I don't know even how to google it properly.
Best regards,
Arkady
For the first time I deal with crossing clock domains (slow-to-fast) and I have faced a problem.
I recieve constant stream of data, which I have to filter, but before processing data have to move from 100 MHz to 240 MHz domain. I used standard asynchronous FIFO approach and I manage to succesfully partition my data and transfer to new domain. Effects are visiable on attached screen shot. The problem is that when I feed that partitioned data into Xilinx FIR Compiler, my outputs signal turns into garbage.
So, my question is how to merge, partitioned by CDC data to obtain stream like before clock conversion? Maybe there are some methods to do so, which I'm not aware of, I will be glad to learn some new techniques and gain more knowledge. I don't know even how to google it properly.
Best regards,
Arkady
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