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    power analysis using synopsys DC compiler

    I am trying to generate power report using Synopsys DC compiler.

    At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command.
    Then I proceeded to analyze the power through DC compiler.

    However, I am getting an warning " There are 1166 objects not found during annotation", and the combinational switching power is showing zero for my design.

    What can be the error?

    I believe the internal signals in the generated SAIF file from the MODELSIM does not match with the internal signals of the synthesized netlist. Do I have to perform postsynthesis simulation, but then how to link the design library file with MODELSIM.


    Kindly guide in this regard.

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    Re: power analysis using synopsys DC compiler

    Quote Originally Posted by avishek_sinha_roy View Post
    I am trying to generate power report using Synopsys DC compiler.

    At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command.
    Then I proceeded to analyze the power through DC compiler.

    However, I am getting an warning " There are 1166 objects not found during annotation", and the combinational switching power is showing zero for my design.

    What can be the error?

    I believe the internal signals in the generated SAIF file from the MODELSIM does not match with the internal signals of the synthesized netlist. Do I have to perform postsynthesis simulation, but then how to link the design library file with MODELSIM.


    Kindly guide in this regard.
    This is a common mistake folks do all the time. Most likely the vcd hierarchy does not match the circuit hierarchy because the VCD was generated when the tb was the top level. DC has the circuit itself as the top level, not its testbench.
    Really, I am not Sam.



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    Re: power analysis using synopsys DC compiler

    Thank you for reply. I understand that since Modelsim is a simulator the test bench should be the top module whereas since the DC is a synthesis tool, the circuit should be top module. But if this is the error then how can I overcome this.



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    Re: power analysis using synopsys DC compiler

    You need to run post synthesis simulation on the synthesized netlist and generate saif file first. Later load the synthesized design and libraries and give generated saif file as an input to design compiler again and run the design. You will generate the power report.



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    Re: power analysis using synopsys DC compiler

    Quote Originally Posted by avishek_sinha_roy View Post
    Thank you for reply. I understand that since Modelsim is a simulator the test bench should be the top module whereas since the DC is a synthesis tool, the circuit should be top module. But if this is the error then how can I overcome this.
    Use the -instance and possibly the -target arguments to the read_saif command to push down to the same level of hierarchy that is used by dc_compiler for synthesis.



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  6. #6
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    Re: power analysis using synopsys DC compiler

    Quote Originally Posted by TonyLS View Post
    Use the -instance and possibly the -target arguments to the read_saif command to push down to the same level of hierarchy that is used by dc_compiler for synthesis.
    I have already used -instance as shown in the following read_saif command.........
    read_saif -input waves.saif -instance test_tb/dut -rtl_direct

    I have not used the -target argument . I am not sure how to use the -target argument. I could not find anything online how to use that.

    - - - Updated - - -

    Quote Originally Posted by vyella1 View Post
    You need to run post synthesis simulation on the synthesized netlist and generate saif file first. Later load the synthesized design and libraries and give generated saif file as an input to design compiler again and run the design. You will generate the power report.
    My problem is not about generating power report. I am able to generate power report using saif file from pre synthesis simulation.

    As suggested, I have also done post synthesis simulation and then used the saif file. However, I am getting similar kind of warning "objects not found during annotation"



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