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    Decoupling CAP using MOSFET?

    Hi everyone!

    Is there any reliability issue when using a MOSFET as a decoupling cap for the supply voltage line?!
    The gate will be connected to vdd, and source/drain will be connected to ground.
    My concern is the gate terminal connected to VDD.

    Thank you very much.

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    Re: Decoupling CAP using MOSFET?

    Huh? Why on earth are you using a MOSFET for a decoupling cap????? Why not use, um, a CAP?

    But assuming for some bizarre reason the only components you have are MOSFETs, you have to be aware of the maximum Vgs.



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    Re: Decoupling CAP using MOSFET?

    "Issue", not really, provided that the supply "is what you
    think it is". Yes, there's gate ox defect density as a long
    term reliability detractor, but it's the same as what you've
    got going on already in a CMOS chip design. You only
    increase the "size of the target" and eat the odds.

    MOSFET Tox is set (you'd like to believe) and process
    tuned / cleaned to get "acceptable" gate ox reliability
    at max rated supply, up to some design limit of gate ox
    area. Now that's all fine, or not, depending on obscured
    details like -

    - what's "acceptable" for reliability, who says so, and is
    -your- customer in agreement?

    - do your application-envelope dimensions violate any of
    the various precepts that the reliability experiments
    analysis took advantage of? Run into this all the time,
    trying to make mil/space "HiRel" parts in commercial
    pure-play foundries; temp range, supply tolerance,
    "other" conditions unanticipated by people in the
    nickel-and-dime, throwaway consumer product fab
    end of the business.

    - Just what is the real gate ox sensitivity to transient
    overstress, how high a spike to what voltage in what
    duration can be withstood how many times? Because
    "2.5V +/- 5% DC" is your "on a good to average day"
    reliability supply envelope but supplies have other
    behaviors and outside "challenges" that you can only
    "put a box around" and tell the customer to respect it
    or pound sand. Which doesn't always go over so well,
    but it's the industry way (only varying in how much
    pain and who gets to taste it).

    Integrated capacitors (non-MOS; MIM, MOM, POP) are
    always (IME) inferior in capacitance density, trading it
    for other interests such as linearity, matching and often
    a need to deposit rather than grow the dielectric. They
    don't give the areal density you want, and they can't
    be "hidden under" low metal levels' local supply routing
    (MIM usually sits higher up, MOM is super not-dense,
    POP requires dual poly which is uncommon except in
    some subset of mixed-signal CMOS flows).


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    Re: Decoupling CAP using MOSFET?

    Quote Originally Posted by barry View Post
    Huh? Why on earth are you using a MOSFET for a decoupling cap????? Why not use, um, a CAP?

    But assuming for some bizarre reason the only components you have are MOSFETs, you have to be aware of the maximum Vgs.
    Simple answer: density. we can get some pF with low area.

    - - - Updated - - -

    Quote Originally Posted by dick_freebird View Post
    "Issue", not really, provided that the supply "is what you
    think it is". Yes, there's gate ox defect density as a long
    term reliability detractor, but it's the same as what you've
    got going on already in a CMOS chip design. You only
    increase the "size of the target" and eat the odds.

    MOSFET Tox is set (you'd like to believe) and process
    tuned / cleaned to get "acceptable" gate ox reliability
    at max rated supply, up to some design limit of gate ox
    area. Now that's all fine, or not, depending on obscured
    details like -

    - what's "acceptable" for reliability, who says so, and is
    -your- customer in agreement?

    - do your application-envelope dimensions violate any of
    the various precepts that the reliability experiments
    analysis took advantage of? Run into this all the time,
    trying to make mil/space "HiRel" parts in commercial
    pure-play foundries; temp range, supply tolerance,
    "other" conditions unanticipated by people in the
    nickel-and-dime, throwaway consumer product fab
    end of the business.

    - Just what is the real gate ox sensitivity to transient
    overstress, how high a spike to what voltage in what
    duration can be withstood how many times? Because
    "2.5V +/- 5% DC" is your "on a good to average day"
    reliability supply envelope but supplies have other
    behaviors and outside "challenges" that you can only
    "put a box around" and tell the customer to respect it
    or pound sand. Which doesn't always go over so well,
    but it's the industry way (only varying in how much
    pain and who gets to taste it).

    Integrated capacitors (non-MOS; MIM, MOM, POP) are
    always (IME) inferior in capacitance density, trading it
    for other interests such as linearity, matching and often
    a need to deposit rather than grow the dielectric. They
    don't give the areal density you want, and they can't
    be "hidden under" low metal levels' local supply routing
    (MIM usually sits higher up, MOM is super not-dense,
    POP requires dual poly which is uncommon except in
    some subset of mixed-signal CMOS flows).
    Thank you very much! you said everything!



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    Re: Decoupling CAP using MOSFET?

    i expect you can get the same or more pF with a capacitor
    and one less lead to connect



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  6. #6
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    Re: Decoupling CAP using MOSFET?

    Quote Originally Posted by wwfeldman View Post
    i expect you can get the same or more pF with a capacitor
    and one less lead to connect
    I have never encountered a technology where a
    capacitor-purpose dielectric is made thinner than the
    lowest voltage MOSFET gate. I'd be interested to see
    any examples otherwise.



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