amr.maghraby
Junior Member level 2
i am using cadence IC 6.13 virtuoso to design an ADC
i am trying to measure the SNR of that ADC , so i build an ideal DAC using Veriloga and take the output of the ADC to the input of the DAC and then i took the output signal from the DAC and export it to the calculator of the Cadence and then i used the spectrum function to find snhr.
there is a relation that relates the sampling frequency , input frequency , no. of cycles , & number of samples in the output signal identified by murmann in his lectures fs/fin = no. of samples/ no. of cycles
the SNR of an ideal 9-bit ADC should be 6.02N+1.76 which will be ≈ 55dB , the problem is that the snhr is only 49 dB , can anyone help me why??
fs = 512MHz , cycles = 3 , no. of samples = 1048576 , fin = 1464.84375 Hz
i am trying to measure the SNR of that ADC , so i build an ideal DAC using Veriloga and take the output of the ADC to the input of the DAC and then i took the output signal from the DAC and export it to the calculator of the Cadence and then i used the spectrum function to find snhr.
there is a relation that relates the sampling frequency , input frequency , no. of cycles , & number of samples in the output signal identified by murmann in his lectures fs/fin = no. of samples/ no. of cycles
the SNR of an ideal 9-bit ADC should be 6.02N+1.76 which will be ≈ 55dB , the problem is that the snhr is only 49 dB , can anyone help me why??
fs = 512MHz , cycles = 3 , no. of samples = 1048576 , fin = 1464.84375 Hz
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