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  1. #1
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    I have problem with my proteus 8.4 simulation

    Here are my simulation errors+messages:

    ISIS Release 8.04.00 (Build 21079) (C) Labcenter Electronics 1990- 2015.
    Compiling design 'C:\Users\admin\Documents\PROTEUS\display.pdsprj'.
    Netlist compilation completed OK.
    Netlist linking completed OK.
    Partition analysis completed OK.
    Simulating partition [52DCF79E]
    PROSPICE 8.04.00 (Build 21003) (C) Labcenter Electronics 1993-2015.
    Loaded netlist 'C:\Users\admin\AppData\Local\Temp\LISA7175.SDF' for design 'display.pdsprj'
    Loaded MODDATA (8192 bytes). [U1_U1]
    Loading binary file 'display.bin'. [U1_U1]
    Logic race condition detected during operating point analysis.
    [SPICE] Gmin step [0 of 120] failed: GMIN=0.001
    [SPICE] Gmin stepping failed
    [SPICE] Source step [0 of 120] failed: source factor = 0.0000
    [SPICE] Too many iterations without convergence.
    Real Time Simulation failed to start.

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  2. #2
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    Re: I have problem with my proteus 8.4 simulation

    The value of resistor R3 is too high.

    Seriously speaking, did you really expect a useful answer just by providing the above information without giving any clue of the schematics?
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  3. #3
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    Re: I have problem with my proteus 8.4 simulation

    Often this type of error is caused by missing grounds, post your Proteus circuit if you want further help.



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  4. #4
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    Re: I have problem with my proteus 8.4 simulation

    Quote Originally Posted by pjmelect View Post
    Often this type of error is caused by missing grounds
    ...which is a specific case of floating nodes.
    As said to OP with other words, the compiler's log by itself is not sufficiently informative.
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