beginner_EDA
Full Member level 4
Hi,
I came across following generated code from vivado:
I know to set parameter inside module we use this way:
some_ip
or use defparam to overreide :
defparam hierarchical_path = paratemter value;
but I didn't understand which kind of syntax is this?
can anybody explain it?
I came across following generated code from vivado:
Code Verilog - [expand] 1 2 3 4 5 6 (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) some_ip some_ip_inst( .a(a), .b(b) );
I know to set parameter inside module we use this way:
some_ip
Code Verilog - [expand] 1 2 3 4 5 6 7 8 #( .EXAMPLE_SIMULATION (1), .SIM_SPEEDUP ("FALSE") ) some_ip_inst( .a(a), .b(b) );
or use defparam to overreide :
defparam hierarchical_path = paratemter value;
but I didn't understand which kind of syntax is this?
Code Verilog - [expand] 1 2 (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *)
can anybody explain it?
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