+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Full Member level 3
    Points: 1,932, Level: 10

    Join Date
    Aug 2013
    Posts
    184
    Helped
    0 / 0
    Points
    1,932
    Level
    10

    verilog set parameter to a module

    Hi,
    I came across following generated code from vivado:

    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    
    (* EXAMPLE_SIMULATION = "1" *) 
      (* SIM_SPEEDUP = "FALSE" *) 
      some_ip some_ip_inst(
     .a(a),
    .b(b)
     );



    I know to set parameter inside module we use this way:
    some_ip
    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    
    #(
            .EXAMPLE_SIMULATION  (1), 
            .SIM_SPEEDUP ("FALSE")
           )
        some_ip_inst(
     .a(a),
    .b(b)
     );

    or use defparam to overreide :
    defparam hierarchical_path = paratemter value;


    but I didn't understand which kind of syntax is this?
    Code Verilog - [expand]
    1
    2
    
    (* EXAMPLE_SIMULATION = "1" *) 
      (* SIM_SPEEDUP = "FALSE" *)
    can anybody explain it?
    Last edited by ads-ee; 20th June 2019 at 15:37. Reason: added code tags

    •   AltAdvertisement

        
       

  2. #2
    Super Moderator
    Points: 31,151, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,188
    Helped
    1705 / 1705
    Points
    31,151
    Level
    43

    Re: verilog set parameter to a module

    The (* some_attribute = some_value *) are for synthesis attributes. Though in this case the attributes don't look like synthesis attributes, they must be custom attributes. They certainly don't show up as attributes in the synthesis guide.



--[[ ]]--