+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Advanced Member level 3
    Points: 5,445, Level: 17
    Achievements:
    7 years registered

    Join Date
    Jan 2012
    Location
    Italy
    Posts
    949
    Helped
    41 / 41
    Points
    5,445
    Level
    17

    guard ring contacts for the PMOS transistors

    Dear friends,

    I usually connect the NWELL substrate contact for the PMOS transistors by putting the NWELL contact only on the right and lift, I am not making it as closed ring as the name indicate. by any way I am verifying that I have no latchup problem

    Also please I have a question, is it good idea to put Substrate contact (GND) beside the PMOS transistors well to make it more reveresed biased

    Thank you very much

    •   AltAdvertisement

        
       

  2. #2
    Full Member level 1
    Points: 1,388, Level: 8

    Join Date
    Mar 2015
    Location
    USA
    Posts
    111
    Helped
    20 / 20
    Points
    1,388
    Level
    8

    Re: guard ring contacts for the PMOS transistors

    I try to fully enclose the tap on the nwell to further reduce the risk of matchup. But if you’re not seeing violations, you might be okay for now. Once you connect to io at top level, you might get latchup violations for having active devices connected to io without a fully enclosed guard ring. Or even violations because those open guard rings are too close to active diffusion contacting io.

    As far as contacting the substrate, it’s a good idea to surround it completely to get a good contact to the substrate.



--[[ ]]--