nidare
Newbie level 6
Hello
I am considering using the topology shown in "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries" for implementing a class AB output stage.
It is stated several places that this topology is suited only for moderately low voltages as the supply voltage is limited by two diode voltages and one vdsat over M20 and M19 in the picture. I guess this depends on the technology used.
I am using a technology with VDD=1.8V and Vtn around 500mV and Vtp around 600mV. I am able to size the transistors, so that all transistors are in saturation when there is no load on the output. When a load is applied, M19 and M20 quickly falls out of saturation. Is this due to the limited voltage margin I have? What condition sets the maximum allowed current draw in this type of circuit?
Is it possible to make this topology work with VDD=1.8V or should I go for another variant?
Thanks.
I am considering using the topology shown in "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries" for implementing a class AB output stage.
It is stated several places that this topology is suited only for moderately low voltages as the supply voltage is limited by two diode voltages and one vdsat over M20 and M19 in the picture. I guess this depends on the technology used.
I am using a technology with VDD=1.8V and Vtn around 500mV and Vtp around 600mV. I am able to size the transistors, so that all transistors are in saturation when there is no load on the output. When a load is applied, M19 and M20 quickly falls out of saturation. Is this due to the limited voltage margin I have? What condition sets the maximum allowed current draw in this type of circuit?
Is it possible to make this topology work with VDD=1.8V or should I go for another variant?
Thanks.