tahirsengine
Member level 3
I am given a task to design a SPI master module in Verilog (The ultimate goal is to design an sensor ASIC).
The problem is: I have only four I/Os i.e. MISO, MOSI, SCLK, and SS(single line).
But on the slave side, I need to control four slaves i.e. EEPROM, an ADC and two digital processing block(can reduce to one).
The question is: How may I control these blocks as slaves using just one SS line. Is there any standard methodology for doing this in ASIC arena?
The problem is: I have only four I/Os i.e. MISO, MOSI, SCLK, and SS(single line).
But on the slave side, I need to control four slaves i.e. EEPROM, an ADC and two digital processing block(can reduce to one).
The question is: How may I control these blocks as slaves using just one SS line. Is there any standard methodology for doing this in ASIC arena?