stanford
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Suppose read/write clk frequencies are EQUAL but are async. What is the minimum depth of async fifo required to stream data through it and why?
Thanks!
Thanks!
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When you say frequency, do you mean ratio of writes to reads? Or are you referring to a FIFO being used to cross clock domains and therefore actually has two clock frequencies?
What are the widths of the data bus on the write side and read side?Suppose read/write clk frequencies are EQUAL but are async. What is the minimum depth of async fifo required to stream data through it and why?
It is a good thing to do. But how much patience do you have to push the OP such that he/she comes out with the right question supplying the right amount amount of info.Maybe some members hate me because I always request specifications....
+1I hate these threads. Everyone assumed a wildly different scenario. All answers might be right, all answers might be wrong. Sigh.
That is perfectly legal. Two clocks can only be sync only if they have the same source and no modification in between. In any other scenario they should be considered async.Suppose read/write clk frequencies are EQUAL but are async
Another question is...
Are the clocks frequency locked, but skewed or truly asynchronous and have the same nominal frequency?
If the clocks are the same nominal frequency but are not from the same source clock then they will drift and your FIFO when written/read from on every clock cycle will eventually over/under flow, which translates to no depth is adequate.
This lack of specifications is an ongoing problem with questions on edaboard. It's the same with many companies and customers. I think it's rare to find someone who asks a "smart question" with enough detail to actually answer their question.
Maybe you have .. but some things still aren`t clear to us because we don´t know all the details of your application.I thought I've given enough info,
Just think about this information.Suppose read/write clk frequencies are EQUAL but are async
Hi,
Maybe you have .. but some things still aren`t clear to us because we don´t know all the details of your application.
Thus we asked for clarification.
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Just think about this information.
Isn´t this information true for every FIFO application? Otherwise you get overflow or underflow...which means data loss.
Klaus
Hi,
please understand, it's impossible to give a good answer without knowing details about your both clocks.
If you need answer:
Please clarify all the doubts and questions we have written..
Klaus