stanford
Full Member level 2
Can you assure that the read clock will never overtake the write clock or vice versa? If not, you need to implement a mechanism for substituting respectively dropping some samples.
- - - Updated - - -
std_match has explained in detail. Not less than two, more likely three or four. Depending on the synchronizer design details.
- - - Updated - - -
If it's a real design question, you can simulate the existing logic. If it's an exercise problem, some information is apparently missing. Or it's an intentionally vague interview question.
#3 already says the two clks are frequency locked. for 100MHz, 2 flops are sufficient for sync. what other info is missing?