switched capacitor circuit layout

Hi team!
I am trying to layout a receiver system using TSMC 65 nm process. The signal (RF) path of the receiver will be Sampled/Hold and go through switched capacitor circuit. The switches are realized by mosfets. Can I please ask a few questions?

Q1: How should I connect the substrate of switch mosfets? I believe I should connect the substrates of switch mosfets separate from the substrates of rf mosfets so that the noisy digital signals would not contaminate the rf mosfet. However, on the switch mosfet, the parasitic caps Cgs will couple the digital signal from the gate to the source, which carries rf signals anyway. So do you think the separate bulk connection is necessary?

Q2: If the separate bulk connection is a good practice, should I also connect the bulk of the capacitors in the switched cap circuit away from the switch mosfet bulk?

Q3: Where should I connect the digital ground to the analog ground? On the top reticule of IC where a lot of small bypass caps are added(as filler cells)? Or out of IC/on PCB where a large bypass cap is added?

Q4: I have a lot of empty area on my top reticule. What should I do with them? Should I fill the area with VDD/GND mesh? Or caps from CDD to Ground?

Thanks
Allen

You can not avoid completely contaminating your signal when you sample. But then on the other hand, you care about the signal that you sample. Hence, you want to have a clean signal at the moment of sampling and after you sample it you don't care how contaminated your source becomes. For best results you can use bottom plate sampling approach which is necessary when you target high linearity. The bulk connection or rather the bulk effect can be greatly mitigated in this case.
If you use a BGA package, I think you can connect the analog and digital grounds outside since there won't be much inductance going from the chip to the PCB.
Filling up with decoupling caps is a good practice.

sutapanaki said:

For best results you can use bottom plate sampling approach which is necessary when you target high linearity. The bulk connection or rather the bulk effect can be greatly mitigated in this case.

Click to expand...

Thanks for your reply! I have thought about bottom plate sampling. For the fastest speed, I unfortunately just use the next stage parasitic caps for the sampling caps. (In my design, the S/H is just for insert a controlled delay so the Cgs process variation doesn't matter that much.)

I thought the bottom plate sampling is for charge injection removal...not for bulk effect. Am I wrong?

Thanks
Allen

Yes, the bottom plate sampling is for mitigating charge injection effects. I thought you were concerned with contaminating your signal with the switching activity and when you switch you inevitably have charge injection. But if you're only concerned with bulk connection then it doesn't hurt to separate the bulks or at least pot guard rings between your rf part and sampler.