kunalsan
Junior Member level 1
hello,
I am trying to design a type-2 charge pump PLL. but there is a problem with PSS simulation in cadence spectre simulation. I am designing PLL with the 19MHz reference frequency and VCO output frequency is 2.5GHz. and I have used divider ratio 128. for divider TSPC latch is used.
please give your kind suggestion.
I am trying to design a type-2 charge pump PLL. but there is a problem with PSS simulation in cadence spectre simulation. I am designing PLL with the 19MHz reference frequency and VCO output frequency is 2.5GHz. and I have used divider ratio 128. for divider TSPC latch is used.
please give your kind suggestion.