ICnow
Newbie level 4
Hello, i have a questions about ESD protection. I was simulating HBM discharge to chip, and looking to voltage on pads. I wanted to check exceeds it breakdown voltage of gate oxide or not. As I understand exist two types of breakdown hard and soft(time-dependent gate oxide breakdown), should i worry if during esd event the voltages in chip exceeds soft breakdown? And should i worry about exceeding hard breakdown voltage, even if it really short? Or i don't need to control voltages at all only currents? And another question if i add to simulation parasitic inductances of bond wire, voltage on pads during esd event start fall with oscillations with huge amplitude(maximum voltage on pads increase from 5V - without inductances, to 40V), should i also worry about that?