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    Analog CMOS Layout Individual Finger Width Sizing

    Hello,

    When doing Analog CMOS Layout, what is the maximum finger individual width that should be used for fingers in MOS layouts ?

    I was told that a maximum size should be less than 20 * Length, so for 65nm that would be 20 * .065 (minimum length) = 1.3 um.

    Others have told me to keep the individual finger width to less than 10 um in size - is there a rule of thumb ?

    This is for matching (inter-digitization and common centroid) layouts.

    Thank you.

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    Re: Analog Layout Finger Size

    For drivers you need to respect current density in the stripe.
    The finger width should be no more than what delivers the
    max allowed current density for the metallization thickness,
    width and any step-coverage compromises.

    For matched devices you care about things like longitudinal
    debiasing, the I*R drops along the stripe subtract from Vgs
    and cause current distribution nonuniformity. You can figure
    the R, should know the I, so can calculate what the I*R drop
    might be and decide whether that is significant to you.

    Neither of these is specific to interdigitated layouts, the
    same applies to simpler styles as well.

    Latly you should look into what the foundry has to say,
    about the valid range of FET W and L for model accuracy.
    There has to be a max or the modeling job is never done.
    I would not lay out a device that the foundry has never
    characterized, unless it was a science project type of
    program (I do a lot of those - but when it's a product on
    a timeline, stick to the trail).



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    Re: Analog Layout Finger Size

    Hello,

    Thanks for replying.

    I would guess that a smaller finger width would lead to a smaller R and hence a small IR drop.

    Does R increase as processes scale per finger width? ie. R increases from 65nm to 40nm to 32nm etc ?

    Thank you.



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    Re: Analog Layout Finger Size

    Current density depends not only on metal line length (= poly width), but also on the current flow pattern in multi-layer metallization, that is determined by the topology of the layout.
    For example, if a metal line is used to route the current vertically (in Z direction), then the lateral current density in the metal is nearly zero, and metal line length is not a factor for EM reliability.

    Also, even if debiasing is no uniform (over poly width, or over device area) - but matched between the two devices - then this non-uniform debiasing will not impact device matching.

    Sheet resistances of metals do increase, in general, with technology scaling (especially strongly starting from ~16nm node).



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    Re: Analog Layout Finger Size

    If you take proper measures you can mitigate those effects.
    However in a library development you might constrain the
    PCells to the "can't possibly screw up" Wmax, if you don't
    trust (or are directed not to) the skill of the eventual user.
    I've seen some kits allow an "override" of such limits (with
    a flag thrown onto every so-check-boxed schematic instance
    so that you get to explain it at design review time).



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