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Capacitor bank design for VCO

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rty94

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Hello I would like to ask which are the steps for designing and testing a capacitor bank in VCO design? I've did an effort but it doesn't seems to work.Thanks in advance!!



eda1.jpgeda2.jpg
 

What would you like to test?
In above figure the source and drain are floating nodes, the ON resistance of the NMOS can be high. I would add parallel PMOS.
You are checking the large signal behaviour of the bank, however it seems you are at the beginning, where a small signal capacitance measure makes more sense.
For this I would do AC simulation next to different switches states and DC voltages between vp and vn nodes, get the current between vp an vn nodes and calculate the capacitance from the imaginary part of it.
 

Could you please explain me the simple initial steps of designing a capacitor bank? I think that there is a part that I didn't understand.. I saw some papers but I don't think but there is no detailed design reference..
 

This is a simple circuit, there are no plans how to design this.
Only function of this to maintain a capacitance value between the two terminals, so you have to check that capacitance for different switch states.
Which part you don't understand? How to measure capacitance? How a switch works? Give more clues, please.
 

I dont understand if I should turn on/off periodically switches for having the appropriate tuning range.. what kind of signals should I apply at b0,b1,b2,b3 to have the desirable TR ?
 

You don't have to switch periodically the switches. Periodically switched capacitors represent resistors with big resistance values. These are used to create high time constants with small device sizes, which makes no sense if you want to design a capacitor bank for a VCO.
For a VCO the tuning range is the minimum-maximum frequency, where you can get the maximum frequency by selecting the smallest capacitance (top branch on your schematic), for minimum frequency you have to select all the capacitance branches at the same time.
Your capacitance values are binary weighted, so with a 4 bit digital code you can sweep the total capacitance value from minimum to maximum in linear steps, and the operating frequency of the VCO will change from maximum to minimum frequency, also in linear steps.
For b0,b1,b2,b3 use DC sources with 0V or VDD, depends on the input digital code.
Point of testing should be that for any 4bit code values from 0001 to 1111 the total capacitance of the bank should change from 1*C to 15*C, and you should check that.
 
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measuring capacitance is by formula imag(Y(1,1))/2/pi/freq via s parameters analysis or there is a better way to do so?
 

simple AC analysis is enough, where you sweep the frequency. calculate imag(IF("/capbank_terminal_name"))/(2*pi*xval(VF("/any_node_name")))
 

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