Alexxk
Junior Member level 3
Hi guys!
I am working on a digital part of a mixed signal design.
I am using LFoundry 150nm technology. When I synthesize my design with a fclock of 1Ghz with the typical library I can meet the timing, but when using the wort lib (not even the worst150degree, the worst just uses a reduced VDD) i get a WNS of -300ps. I am still a beginner in ASIC design but what I have read here so far is that it is common practice to use the worst lib for synthesis. Can I trust my circuit to work at 1Ghz If I take care that the VDD doesnt drop so the cells behave like the typical lib describes? Since this is a academic project, would be an increase in VDD a solution (to get to the parameters of the BEST library)?
I allready identified the critical path, so the worst case would be to alter my design there perform that calculations in two clock cylces, but nevertheless I would liek to have a deeper understanding about synthesis and which libs to use!
Thank you very much!
Alex
I am working on a digital part of a mixed signal design.
I am using LFoundry 150nm technology. When I synthesize my design with a fclock of 1Ghz with the typical library I can meet the timing, but when using the wort lib (not even the worst150degree, the worst just uses a reduced VDD) i get a WNS of -300ps. I am still a beginner in ASIC design but what I have read here so far is that it is common practice to use the worst lib for synthesis. Can I trust my circuit to work at 1Ghz If I take care that the VDD doesnt drop so the cells behave like the typical lib describes? Since this is a academic project, would be an increase in VDD a solution (to get to the parameters of the BEST library)?
I allready identified the critical path, so the worst case would be to alter my design there perform that calculations in two clock cylces, but nevertheless I would liek to have a deeper understanding about synthesis and which libs to use!
Thank you very much!
Alex